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C-COR Cuts DSP Development Time by 30 Percent Using Simulink and Parallel Computing Toolbox

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C-COR’s QAM modulator.

"With Simulink and Parallel Computing Toolbox, we simulated and analyzed different filter topologies and hundreds of filter types in our architecture. Because the simulations were so fast, we were able to evaluate—and ultimately use—filter types that we would not normally even consider."

Jim Failla, C-COR

As cable operators continue to expand their video-on-demand, Internet, and standard cable television offerings, they face considerable pressure to reduce operational expenses. With head-end space at a premium, operators need high-density systems that can provide advanced functionality with minimal consumption of rack space and power.

C-COR is a global provider of network solutions that deliver advanced voice, video, and data. Engineers at C-COR use MathWorks tools to develop high-density edge quadrature amplitude modulation (QAM) systems that convert video content and Internet data into signals used by home set-top boxes and cable modems. MathWorks tools enable C-COR to reduce costs by simulating multiple design options and verifying the system before committing it to VHDL code.

"The QAM modulator is a fairly complex product," says Jim Failla, development engineer at C-COR. "MathWorks tools enable us to develop our architecture in a simulation environment, where we can debug, improve, and verify it before implementing on hardware."

Challenge

C-COR needed to develop a QAM system that complied with stringent International Telecommunications Union (ITU) standards, including ITU-T J.83/B. “We are developing a high-density and low power-consumption solution,” explains Failla. “To achieve this, we need spot-on filtering. We have multiple banks of digital filtering, numerous different filter topologies, and various roll-offs for the filters. The challenge is finding the optimal topology, filter types, and filter values as quickly as possible.”

In the past, C-COR implemented designs in VHDL before downloading the code to an FPGA for debugging and testing. To minimize tuning and debugging time, C-COR’s goal was to do 90% of the debugging for the QAM modulator in the simulation environment rather than in the lab.

Solution

C-COR engineers used MathWorks tools to design the QAM modulator, verify it through simulation, and rapidly find a set of filters that met the system’s performance objectives.

Dean Painchaud, principal engineer at C-COR, worked with Failla and other C-COR engineers to develop the system architecture. Using Simulink®, Communications System Toolbox™, and Signal Processing Toolbox™ software, Failla then implemented the architecture as a detailed circuit-level model.

Failla used DSP sources, communications filters, and the QAM Modulator block from Communications System Toolbox to produce a baseband representation of the QAM modulated signal. He used Signal Processing Toolbox to design and analyze finite impulse response (FIR) digital filters.

Failla attended a MathWorks training course on writing advanced S-functions to customize Simulink blocks. “The course provided in-depth understanding. It was very helpful,” he notes.

Failla wrote S-functions to implement a form of fractional resampling that matched QAM 256 data rates to ITU specifications.

After running simulations to debug the system and confirm that it met performance specifications, the team used Simulink to demonstrate the system to senior management and secure approval to move forward.

To optimize the system, C-COR engineers needed to evaluate several filter topologies and dozens of filter types and values. They used Parallel Computing Toolbox™ software to accelerate this process by running simulations concurrently on an eight-node computer cluster assembled from decommissioned machines.

Using the MathWorks Job Manager in Parallel Computing Toolbox, Failla scheduled and executed hundreds of simulation runs. He automated the process by altering parameterized filter values through scripts and setting the system to notify him when performance objectives were met.

Once the system was fully verified and optimized in Simulink, C-COR engineers translated it to VHDL for implementation on an FPGA. C-COR is working on new versions of the QAM modulator that comply with ITU-T J.83/A and C for European and Japanese markets.

“Our use of Simulink has enabled us to shave significant time off of our design schedule. Building new versions takes just weeks now, instead of months. With shorter cycles, we are able to develop intellectual property for more projects. This is a major advantage for C-COR, in that we have full control over the design process and, at the same time, have been able to extend coverage to more projects than before,” says Failla.

Results

  • Design time shortened by 30 percent. “Using MathWorks tools we achieved the results we were looking for in three or four months less than it would normally have taken,” says Failla. “From conception to implementation, we would have needed about 10 months without MathWorks tools.”
  • Lab time reduced from weeks to days. “We surpassed our goal of doing 90% of the debugging in Simulink. The first time we targeted the FPGA we had our design up and running in five days, a task that used to take three weeks or more. Because we had verified the system in Simulink, we knew that any remaining problems were due to the VHDL implementation, not the architecture,” says Failla. “The simulation results were very accurate—only 1 or 2 dB off from what we actually saw in the lab.”
  • System optimization accelerated. “With Simulink and Parallel Computing Toolbox on an eight-node cluster, we ran eight simulations in the same time that it takes to do one,” says Failla. “This enabled us to run hundreds of simulations to find the best filter topology and values, leading to a 10-15 dB performance improvement.”

Challenge

To develop a high-density edge QAM modulator for on-demand cable service providers

Solution

Use MathWorks tools to evaluate architectural alternatives and design, simulate, and verify the system

Results

  • Design time shortened by 30 percent
  • Lab time reduced from weeks to days
  • System optimization accelerated

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