Third-Party Products & Services


High-level synthesis for DSP design


  • Provides an automated path from MATLAB to FPGA and ASIC design flows
  • Inputs MATLAB models and Simulink designs
  • Performs automated floating- to fixed-point conversion
  • Generates synthesizable RTL models (VHDL/Verilog) and simulation testbenches
  • Produces optimized RTL models based on the target FPGA device
  • Interfaces to FPGA vendor tools


Xilinx's high-level DSP synthesis tool provides a direct path from the MATLAB technical design language to industry-standard FPGA and ASIC design flows for DSP designers. With AccelDSP, designers can easily load DSP algorithms as script MATLAB code and the tool automatically determines the design's structure and provides an intuitive debugging environment. AccelDSP automatically performs floating- to fixed-point conversion and then produces synthesizable RTL (VHDL, Verilog) models and simulation testbenches to eliminate the time-consuming and error-prone manual creation process. AccelDSP uses the Resource Description Language (RDL) to optimize the creation of RTL models based on the resources available within the targeted FPGA device.
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Xilinx, Inc.

2100 Logic Dr
San Jose, CA 95124-3450
Tel: 408-559-7778
Fax: 408-626-6440

Required Products


  • Windows


  • Consulting
  • E-mail
  • Fax
  • Telephone
  • Training

Product Type

  • Data Analysis Tools


  • Image Processing and Computer Vision
  • Real-Time Systems
  • Digital Signal Processing


  • Aerospace and Defense
  • Automotive
  • Computer Electronics
  • Communication Infrastructure
  • Consumer Electronics
  • Semiconductor