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Verifying Floating-Point IP Cores on FPGAs with MATLAB & Simulink

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Robert Anderson, MathWorks

Learn how you can use MATLAB and Simulink with FPGA development boards to verify hardware implementations of algorithm models.

MathWorks and Altera engineers show how HDL Verifier can be used with FPGA development boards to run test scenarios faster and verify implementations in real hardware. In this webinar, we demonstrate hardware verification of a floating-point Cholesky decomposition IP core, with the test bench running as a MATLAB/Simulink model and the design-under-test running on Altera development boards.

You'll learn details about floating-point IP cores from Altera that are available with Altera DSP Builder. Then we use demonstrations to show how HDL Verifier can be used with standard FPGA development boards, and how you can use built-in wizards in HDL Verifier to configure it to run with your own custom FPGA board.

About the presenters:

Robert Anderson is a Principal Application Engineer for signal processing and communications at MathWorks, with a focus on FPGA implementation.  Robert has over 25 years of experience in hardware design and implementation. He earned his MS. in electrical and computer engineering from Northwestern University.

Udayan Sinha is a Product Marketing Engineer focusing on digital signal processing solutions at Altera. He holds a BSEE from the University of California, Davis.

Product Focus

  • HDL Verifier
  • HDL Coder

Registrato: 31 ott 2012