By combining MATLAB® and Simulink® with third-party products, engineers can develop and deploy motor control applications using Model-Based Design. They can design control algorithms graphically in Simulink and then simulate them alongside high-fidelity models of motors and blocks representing controller hardware peripherals. After validating their algorithms via simulation, engineers can generate C or HDL code from the algorithms to run on MCU or DSP controller hardware, synthesize to FPGAs, or deploy on SoC architectures.
NXP’s Model-Based Design Toolbox is a toolchain for configuring and generating software to execute motor control algorithms on NXP MCUs. The toolbox provides a Simulink blockset for peripheral devices such as PWM, A/D, and CAN, as well as an optimized motor control blockset that includes functions such as Park/Clarke transforms and digital filters. The blocksets are integrated with an Embedded Coder® target for generating and deploying code onto NXP controllers and performing software-in-the-loop and processor-in-the-loop testing.
Microchip provides blocksets that allow the simulation of motor control algorithms running on dsPIC® digital signal controllers. The Motor Control Library Blockset contains Simulink blocks for motor control applications, including reference frame transforms, a proportional-integral controller, and trigonometric functions. The Motor Model Library adds a Simulink model for simulating permanent-magnet synchronous motors (PMSMs). For deploying control algorithms onto dsPIC hardware, Microchip’s MPLAB® Device Blocks for Simulink provide peripheral blocks for digital/analog I/O, counters and timers, pulse width modulation (PWM) motor control, and more. You can add and configure these blocks in Simulink models and then generate C/C++ code to run on dsPIC/PIC devices.
Intel provides motor control tools to target both conventional FPGAs and SoC FPGAs that combine programmable logic with an ARM® hard processor. You can design control algorithms in Simulink and then use either HDL Coder™ or Intel’s DSP Builder for Intel FPGAs to generate HDL code for Intel® FPGAs. Using Embedded Coder and related support packages you can generate C/C++ code for the ARM cores on FPGA SoC platforms. Intel’s Drive-on-a-Chip reference design includes Simulink models of motor control algorithms and physical models of motors for system simulation and VHDL code generation. The reference design supports Intel MAX 10 and Cyclone® V FPGAs as well as Cyclone V SoC FPGAs, with built-in support for motor control development kits.
JMAG finite element analysis software is used for developing electromechanical equipment such as motors, power converters, and actuators. JMAG can simulate magnetic flux density and electromagnetic forces in a range of motors, including permanent magnet, induction, and stepper motors. JMAG-RT extracts motor features as a precise reduced-order model provided as a Simulink block for motor control development. High-fidelity JMAG-RT models capture device performance, including nonlinear effects, saturation, and space harmonics.