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Use Deep Learning on FPGA Bitstreams

The Deep Learning HDL Toolbox™ hardware support packages provide bitstreams that you can use to deploy various deep learning networks on the target platform.

This table illustrates the mapping between the target boards, data types, and bitstream names.

Target BoardData TypeBitstream Name

Xilinx® Zynq® -7000 ZC706

single'zc706_single'

Xilinx Zynq-7000 ZC706

int8'zc706_int8'

Xilinx Zynq UltraScale™ ZCU102

single'zcu102_single'

Xilinx Zynq UltraScale ZCU102

int8'zcu102_int8'

Intel® Arria® 10 SoC development kit

single'arria10soc_single'

Intel Arria 10 SoC development kit

int8'arria10soc_int8'

For an example that illustrates how you can use these bitstreams names and deploy your network when running the workflow, see Prototype Deep Learning Networks on FPGA and SoCs Workflow.