FIL Simulation with CLI Commands for MATLAB

R2026b

FIL Overview

FPGA-in-the-Loop (FIL) enables verification of generated HDL on physical FPGA hardware while MATLAB^® drives input stimulus and reads output results. In this workflow, MATLAB code is first converted to fixed-point, HDL Coder™ generates HDL code for the design under test (DUT) and generates the FIL infrastructure and MATLAB System object™ used for board communication.

The workflow in this section uses Arrow^® DECA MAX^® 10 FPGA evaluation kit. Use hdlsetuptoolpath if the FPGA design software path is not already configured. To set up your FPGA board and machine to communicate for FIL simulation, see Step 1. Set Up FPGA Development Board (SoC Blockset). Before programming or running FIL simulation, verify that the FPGA board is powered on, connected, and reachable from the host machine. To generate FIL artifacts and run an FIL simulation, you can use the coder.HdlConfig.

Configure HDL Code Generation

Create an HDL code generation configuration object and set the target HDL language, workflow, rate handling, and traceability options.

hdlcfg = coder.config("hdl");
hdlcfg.EnableRate = "DUTBaseRate";
hdlcfg.EnableTraceability = true;
hdlcfg.TargetLanguage = "Verilog";
hdlcfg.Workflow = "Generic ASIC/FPGA";

Configure FPGA-in-the-Loop Settings

Enable FIL test bench generation and specify the target board, communication interface, board network settings, and synthesis tool.

hdlcfg.GenerateFILTestBench = true;
hdlcfg.FILBoardName = "Arrow DECA MAX 10 FPGA evaluation kit";
hdlcfg.FILBoardIPAddress = "192.168.0.2";
hdlcfg.FILBoardMACAddress = "00-0A-35-02-21-8A";
hdlcfg.FILConnection = "JTAG";
hdlcfg.SynthesisTool = "Altera Quartus II";
hdlcfg.FILLogOutputs = true;

Configure Fixed-Point Conversion

Create a fixed-point configuration object and specify the MATLAB test bench used to collect range information and validate the fixed-point proposal.

fixptcfg = coder.config("fixpt");
fixptcfg.TestBenchName = "mlhdlc_sysobj_ex_tb";

Generate Fixed-Point Code, HDL, and FIL Artifacts

Run code generation using the fixed-point configuration and the HDL configuration. This command analyzes the floating-point MATLAB design, proposes fixed-point types, generates fixed-point MATLAB code, generates Verilog HDL, and creates the FIL test bench infrastructure.

codegen -float2fixed fixptcfg -config hdlcfg mlhdlc_sysobj_ex

The FIL generation step creates MATLAB entry points, HDL wrapper files, communication components, and the target FPGA project.

Run FPGA Implementation and Generate Programming File

During FIL generation, the workflow creates a Quartus^® project and runs implementation for the selected FPGA device. The implementation flow completes synthesis, optimization, placement, physical optimization, routing, timing report generation, and bitstream generation. The generated programming file is:

<project_root>/codegen/mlhdlc_sysobj_ex/fil/mlhdlc_sysobj_ex_fixpt_fil/mlhdlc_sysobj_ex_fixpt_fil.bit

Instantiate the Generated FIL System Object

After code generation completes, add the generated FIL folder to the MATLAB path and instantiate the generated System object

addpath('<project_root>/codegen/mlhdlc_sysobj_ex/fil') 
filObj = class_mlhdlc_sysobj_ex_fixpt_sysobj;

The generated object contains the interface metadata required for FIL simulation, including DUT name, input and output signal widths, output data types, board name, vendor, synthesis tool, programming file, and scan chain position.

Program the FPGA

Program the FPGA with the generated bitstream before running FIL simulation.

programFPGA(filObj);

Confirm that the board is connected and that the network settings match the configured board IP address and MAC address.

Run FIL Simulation from MATLAB

Use the generated System object as a MATLAB function. Provide inputs that match the generated input interface and read the returned FPGA outputs.

[y1, y2] = filObj(u1, u2, u3, u4, u5);

For convenience, the generated workflow also provides a test bench execution function. This function programs or uses the generated interface and runs the FIL test bench sequence.

run_mlhdlc_sysobj_ex_fixpt_fil

When simulation is complete, release the System object and associated hardware resources.

release(filObj);

Summary

This workflow generates a complete customer-ready FPGA-in-the-Loop verification setup from MATLAB code. The flow converts the MATLAB algorithm to fixed-point, generates Verilog HDL code, creates FIL infrastructure, builds the FPGA programming file in Quartus, generates a MATLAB System object, and enables hardware execution of the DUT directly from MATLAB.

You can use the final generated programming file and System object to program the FPGA and run FIL simulation using either the generated test bench function or direct System object calls.