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Enable HDL DUT output port generation for test points

Enable creation of DUT output ports for the test point signals

Model Configuration Pane: Global Settings / Ports

Description

Enable this setting to create DUT output ports for the test point signals in the generated HDL code.

Settings

off (default) | on

Default: Off

on

When you enable this setting, the code generator creates DUT output ports for the test point signals in the generated HDL code. You can observe the test point signals and debug your design by connecting a Scope block to the output ports corresponding to these signals.

off

When you disable this setting, the code generator preserves the test point signals and does not create DUT output ports in the generated HDL code.

Note

When you designate test points for states inside a Stateflow® Chart, the code generator ignores this setting.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir DUT subsystem, to generate DUT output ports in the HDL code, use either of these methods:

  • Pass the property as an argument to the makehdl function.

    makehdl ('sfir_fixed/symmetric_sfir','EnableTestpoints','on')

  • When you use hdlset_param, you can set the parameter on the model, and then generate HDL code by using makehdl.

    hdlset_param('sfir_fixed','EnableTestpoints','on')
makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: EnableTestpoints
Type: character vector
Value: 'on' | 'off'
Default: 'off'

Version History

Introduced in R2017b

See Also