hdlcoder.ReferenceDesign Class

R2026b

Namespace: hdlcoder

Reference design registration object that describes SoC reference design

Description

refdesign = hdlcoder.ReferenceDesign("SynthesisTool", toolname) creates a reference design object that you use to register a custom reference design for an SoC platform.

To specify the characteristics of your reference design, set the properties of the reference design object.

Use a reference design tool version that is compatible with the supported tool version. If you choose a different tool version, it is possible that HDL Coder™ is unable to create the reference design project for IP core integration.

Creation

refdesign = hdlcoder.ReferenceDesign("SynthesisTool",toolname) creates a reference design for the synthesis tool toolname.

Input Arguments

toolname — Synthesis tool name

Xilinx Vivado (default) | Altera Quartus II | Xilinx ISE | Microchip Libero SoC

Synthesis tool name, specified as a character vector.

Example: 'Altera Quartus II'

Properties

ReferenceDesignName — Reference design name

'' (default) | character vector | string

Reference design name, specified as a character vector or string. In the HDL Workflow Advisor, this name appears in the Reference design drop-down list.

Example: 'Default system (Vivado 2015.4)'

ReferenceDesignInfo — Reference design information

'' (default) | character vector | string

Since R2026b

Reference design information, specified as a character vector or string. Use this property to provide descriptive information about the selected reference design, such as the board, clock, synthesis tool, interface, plugin, and author information.

You can view the reference design information in the HDL Workflow Advisor by clicking More info in the Set Target Reference Design task when the Target workflow parameter is IP Core Generation. Alternatively, in the Configuration Parameters dialog box, in the HDL Code Generation > Target pane, in the Reference Design Settings section, click More info.

This table describes the supported values for ReferenceDesignInfo and the action performed when you click More info.

ReferenceDesignInfo Value	Description	Action When You Click More info
Web URL	Specify a valid URL.	Opens the URL in the default web browser.
PDF file name	Specify the name of a PDF file located in the reference design plugin folder.	Opens the PDF file in the default application or browser.
HTML file name	Specify the name of an HTML file located in the reference design plugin folder.	Opens the HTML page in MATLAB®.
Plain text description	Provide a text description of the reference design.	Opens an HTML page in MATLAB that contains your text, followed by reference design metadata, such as the board, clock, synthesis tool, and author information.
Empty value	Do not specify any value.	Opens an HTML page in MATLAB that summarizes the reference design metadata, such as board, clock, synthesis tool, and author information.

Note

If you specify a file name, the file must be in the reference design plugin folder. The software generates an error if the specified file does not exist or if the file format is unsupported.

Example: hRD.ReferenceDesignInfo = "This reference design demonstrates AXI-based data transfer on a Zynq-based system."

Example: hRD.ReferenceDesignInfo = "default_system_info.pdf"

BoardName — Board name

'' (default) | character vector

Board associated with this reference design, specified as a character vector.

Example: 'Enclustra Mars ZX3 with PM3 base board'

SupportedToolVersion — Supported tool version

{} (default) | cell array of character vectors

One or more tool versions that work with this reference design, specified as a cell array of character vectors.

Example: {'2020.2'}

Example: {'13.7','14.0'}

CustomConstraints — Design constraint file (optional)

{} (default) | cell array of character vectors

One or more design constraint files, specified as a cell array of character vectors. This property is optional. You must place the custom constraint file inside a reference design package folder which is at the same folder level as the reference design plugin file, plugin_rd.m. When you run the IP Core Generation Workflow, HDL Coder copies these files to the synthesis tool's project folder.

Example: {'MarsZX3_PM3.xdc'}

Example: {'MyDesign.qsf'}

CustomFiles — Relative path to required file or folder (optional)

{} (default) | cell array of character vectors

One or more relative paths to files or folders that the reference design requires, specified as a cell array of character vectors. This property is optional.

Examples of required files or folders:

• Existing IP core used in the reference design.

  For example, if the IP core, my_ip_core, is in the reference design folder, set CustomFiles to {'my_ip_core'}

• PS7 definition XML file.

  For example, to include a PS7 definition XML file, ps7_system_prj.xml, in a folder, data, set CustomFiles to {fullfile('data', 'ps7_system_prj.xml')}

• Folder containing existing IP cores used in the reference design. HDL Coder supports only a specific IP core folder name for each synthesis tool:

  • For Altera^® Qsys, IP core files must be in a folder named ip. Set CustomFiles to {'ip'}.

  • For Xilinx^® Vivado^®, IP core files, or a zip file containing the IP core files, must be in a folder named ipcore. Set CustomFiles to {'ipcore'}.

  • For Xilinx EDK, IP core files must be in a folder named pcores. Set CustomFiles to {'pcores'}.

Note

To add IP modules to the reference design, it is recommended to create an IP repository folder that contains these IP modules, and then use the addIPRepository method.

You must place the custom constraint file inside a reference design package folder which is at the same folder level as the reference design plugin file, plugin_rd.m. When you run the IP Core Generation Workflow, HDL Coder copies these files to the synthesis tool's project folder.

Example: {'my_ip_core'}

Example: {fullfile('data', 'ps7_system_prj.xml')}

Example: {'ip'}

Example: {'ipcore'}

Example: {'pcores'}

DeviceTreeName — Linux device tree name

character vector

Specify the device tree file name. For an example that shows how to use different device tree file names when mapping the DUT ports to different AXI4-Stream channels, see Use Callback Functions in Custom Reference Design.

Example: 'devicetree_axistream_iio.dtb'

AddMATLABAXIManagerParameter — Control visibility of Insert AXI Manager parameter

'true' (default) | 'false' | logical data type

Control visibility of the Insert AXI Manager (HDL Verifier required) parameter in the Set Target Reference Design task of the HDL Workflow Advisor. By default, the property value is 'true', which means that the parameter is visible in the Set Target Reference Design task. To disable the parameter, set the property value to 'false'.

After you enable this property, to specify whether you want the code generator to insert the AXI manager IP, use the MATLABAXIManagerDefaultValue property.

This property is optional.

Example: 'false'

MATLABAXIManagerDefaultValue — Specify whether to insert AXI manager IP

'off' (default) | 'JTAG' | 'PL Ethernet' | character vector

Specify whether you want the code generator to insert the AXI manager IP. The values that you specify are the choices for the Insert AXI Manager (HDL Verifier required) drop-down in the Set Target Reference Design task of the HDL Workflow Advisor. To specify insertion of the AXI manager IP automatically, before you set this property, set the AddMATLABAXIManagerParameter property to 'true'.

This property is optional. Set this property to one of these values.

• 'off' — Disable insertion of the AXI manager IP.

• 'JTAG' — Enable AXI manager IP insertion for the JTAG connection. This value inserts the AXI Manager IP into your reference design.

• 'PL Ethernet' — Enable AXI manager IP insertion for the programmable logic (PL) Ethernet connection. This value inserts the UDP AXI Manager IP into your reference design.

Example: 'JTAG'

IPCacheZipFile — IP cache file to include in the project

'' (default) | 'ipcache.zip' | character vector

Specify the IP cache zip file to include in your project. When you run the IP Core Generation workflow in the HDL Workflow Advisor, the code generator extracts this file in the Create Project task. The Build FPGA Bitstream task reuses the IP cache, which accelerates reference design synthesis.

This property is optional.

Example: 'ipcache.zip'

ReportTimingFailure — Report timing failures as warnings or errors

'hdlcoder.ReportTiming.Warning' (default) | 'hdlcoder.ReportTiming.Error'

Specify whether you want the code generator to report timing failures in the Build FPGA Bitstream task as warnings or errors. When you run the IP Core Generation workflow in the HDL Workflow Advisor, by default, the code generator reports any timing failures as error. If you have implemented the custom logic to resolve timing failures, you can specify these failures to be reported as warning instead of error. To learn more, see Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows.

This property is optional.

Example: 'hdlcoder.ReportTiming.Warning'

HasProcessingSystem — Specify if reference design has existing Processing System (PS)

true (default) | false | logical data type

Specify whether the reference design contains a processing system (PS) IP. Set to true if the reference design targets an SoC platform with an embedded processor. Set to false if the reference design targets a standalone FPGA board without a processing system.

Example: 'false'

GenerateIPCoreDeviceTreeNodes — Enable generation of device tree nodes for HDL Coder IP core

false (default) | true | logical data type

Enable generation of device tree nodes for an HDL Coder generated IP core, and then insert the nodes into the device tree. To enable the generation of device tree nodes for the IP core, HasProcessingSystem must be set to true.

Do not enable this property if you do not need any additional device tree nodes to be inserted into the registered device tree for the generated IP core.

Example: 'true'

ResourcesUsed — Board resources used by reference design

structure

Board resources used by reference design, returned as a structure with the fields:

LogicElements — Reference design resources utilized by FPGA lookup tables (LUTs)

0 (default)

Reference design resources utilized by FPGA lookup tables (LUTs), specified as a number.

Example: hRD.ResourcesUsed.LogicElements = 100

DSP — Reference design resources utilized by FPGA DSP slices

0 (default)

Reference design resources utilized by FPGA DSP slices, specified as a number.

Example: hRD.ResourcesUsed.DSP = 3

RAM — Reference design resources utilized by FPGA board RAM resources

0 (default)

Reference design resources utilized by FPGA board RAM resources, specified as a number.

Example: hRD.ResourcesUsed.RAM = 32000

Methods

Public Methods

CallbackCustomProgrammingMethod	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
CustomizeReferenceDesignFcn	Function handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor
PostBuildBitstreamFcn	Function handle for callback function that gets executed after the build FPGA bitstream task runs
PostCreateProjectFcn	Function handle for callback function that gets executed after the create project task runs
PostGenerateIPCoreFcn	Function handle for callback function that executes after IP core generation runs
PostSWInterfaceFcn	Function handle for custom callback function that gets executed after the generate software interface task runs
PostTargetInterfaceFcn	Function handle for callback function that gets executed after the set target interface task runs
PostTargetReferenceDesignFcn	Function handle for callback function that gets executed after the target reference design is set
addAXI4MasterInterface	Add and define AXI4 Master interface
addRegisterInterface	Add and define register interface using AXI4 and AXI4-Lite protocol
addAXI4StreamInterface	Add AXI4-Stream interface
addAXI4StreamVideoInterface	Add AXI4-Stream Video interface
addClockInterface	Add clock and reset interface
addCustomEDKDesign	Specify Xilinx EDK MHS project file
addCustomQsysDesign	Specify Altera Qsys project file
addCustomVivadoDesign	Specify Xilinx Vivado exported block design Tcl file
addCustomLiberoDesign	Specify Microchip Libero SoC exported block design Tcl file
addDeviceTree	Add device tree for reference design object
addIncludeFolder	Specify a folder path for device tree include files and interface-specific fragment files
addFPGADataCaptureInterface	Add and define FPGA Data Capture interface
addIncludeFolder	Specify a folder path for device tree include files and interface-specific fragment files
addInternalIOInterface	Add and define internal IO interface between generated IP core and existing IP cores
addIPRepository	Include IP modules from your IP repository folder in your custom reference design
addParameter	Add and define custom parameters for your reference design
validateReferenceDesign	Check property values in reference design object

Version History

Introduced in R2015a