Clock and Reset Input Parameters for Testbench

This page describes configuration parameters that reside in the HDL Code Generation > Test Bench tab of the Configuration Parameters dialog box. Using the parameters in this tab, you can specify the clock high time, clock low time, and whether you want the test bench to force clock, reset, and clock enable input signals.

Force clock

Specify whether the test bench forces clock input signals.

Settings

Default: On

On

The test bench forces the clock input signals. When this option is selected, the clock high and low time settings control the clock waveform.

Off

A user-defined external source forces the clock input signals.

Dependencies

This property enables the Clock high time and Clock high time options. This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: ForceClock

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'ForceClock', 'off')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'ForceClock', 'off')
  makehdltb('sfir_fixed/symmetric_fir')

Clock high time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals high (1).

Settings

Default: 5

Specify a positive integer value. The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Dependency

This parameter is enabled when Force clock is selected.

Command-Line Information

Property: ClockHighTime

Type: integer

Value: positive integer

Default: 5

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'ClockHighTime', 2)

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'ClockHighTime', 2)
  makehdltb('sfir_fixed/symmetric_fir')

Clock low time (ns)

Specify the period, in nanoseconds, during which the test bench drives clock input signals low (0).

Settings

Default: 5

The Clock high time and Clock low time properties define the period and duty cycle for the clock signal. Using the defaults, the clock signal is a square wave (50% duty cycle) with a period of 10 ns.

Dependency

This parameter is enabled when Force clock is selected.

Command-Line Information

Property: ClockLowTime

Type: integer

Value: positive integer

Default: 5

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'ClockLowTime', 2)

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'ClockLowTime', 2)
  makehdltb('sfir_fixed/symmetric_fir')

Force clock enable

Specify whether the test bench forces clock enable input signals.

Settings

Default: On

On

The test bench forces the clock enable input signals to active-high (1) or active-low (0), depending on the setting of the clock enable input value.

Off

A user-defined external source forces the clock enable input signals.

Dependencies

This property enables the Clock enable delay (in clock cycles) option.

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: ForceClockEnable

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'ForceClockEnable', 'off')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'ForceClockEnable', 'off')
  makehdltb('sfir_fixed/symmetric_fir')

Clock enable delay (in clock cycles)

Define elapsed time (in clock cycles) between deassertion of reset and assertion of clock enable.

Settings

Default: 1

The Clock enable delay (in clock cycles) property defines the number of clock cycles elapsed between the time the reset signal is deasserted and the time the clock enable signal is first asserted. In the figure below, the reset signal (active-high) deasserts after 2 clock cycles and the clock enable asserts after a clock enable delay of 1 cycle (the default).

In the figure below, the reset signal (active-high) de-asserts after the interval labelled Hold Time. The clock enable asserts after a further interval labelled Clock enable delay.

Dependency

This parameter is enabled when Force clock enable is selected.

Command-Line Information

Property: TestBenchClockEnableDelay

Type: integer

Default: 1

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'TestBenchClockEnableDelay', 2)

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'TestBenchClockEnableDelay', 2)
  makehdltb('sfir_fixed/symmetric_fir')

Force reset

Specify whether the test bench forces reset input signals.

Settings

Default: On

On

The test bench forces the reset input signals.

Off

A user-defined external source forces the reset input signals.

Tips

If you select this option, you can use the Hold time option to control the timing of a reset.

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: ForceReset

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'ForceReset', 'off')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'ForceReset', 'off')
  makehdltb('sfir_fixed/symmetric_fir')

Reset length (in clock cycles)

Define length of time (in clock cycles) during which reset is asserted.

Settings

Default: 2

The Reset length (in clock cycles) property defines the number of clock cycles during which reset is asserted. Reset length (in clock cycles) must be an integer greater than or equal to 0. The following figure illustrates the default case, in which the reset signal (active-high) is asserted for 2 clock cycles.

Dependency

This parameter is enabled when Force reset is selected.

Command-Line Information

Property: Resetlength

Type: integer

Default: 2

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdltb function.

  makehdltb('sfir_fixed/symmetric_fir', ... 
              'Resetlength', 4)

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

  hdlset_param('sfir_fixed', 'Resetlength', 4)
  makehdltb('sfir_fixed/symmetric_fir')