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Diagnostic Parameters for Reals and Black Box Interfaces

This section contains parameters in the Diagnostics option under Advanced tab in the Configuration Parameters dialog box. Select HDL Code Generation > Global Settings. To check for name conflicts in black box interfaces and for the presence of reals in the generated HDL code, use these parameters.

Check for name conflicts in black box interfaces

Specify whether to check for duplicate module or entity names in generated HDL code and black box interface HDL code.

Settings

Default: Warning

None

Do not check for black box subsystems that have the same HDL module name as a generated HDL module name.

Warning

Check for black box subsystems that have the same HDL module name as a generated HDL module name. Display a warning if matching names are found.

Error

Check for black box subsystems that have the same HDL module name as a generated HDL module name. Display an error if matching names are found.

Command-Line Information

Property: DetectBlackBoxNameCollision
Type: character vector
Value: 'None' | 'Warning' | 'Error'
Default: 'Warning'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','DetectBlackBoxNameCollision','None')
    makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','DetectBlackBoxNameCollision','None')

See Also

Check for presence of reals in generated HDL code

Specify whether to check for reals in the generated HDL code.

Settings

Default: Error

None

Do not check for reals in the generated HDL code.

Warning

Checks and warns of presence of real data types in the generated HDL code. Real data types in the generated HDL code are not synthesizable on target FPGA devices.

Error

Checks and generates an error if the generated HDL code uses real data types. If you are generating code for simulation purposes and not for synthesizing your design, you can change this setting to Warning or None. To generate synthesizable HDL code, set the Floating Point IP Library to Native Floating Point.

Command-Line Information

Property: TreatRealsInGeneratedCodeAs
Type: character vector
Value: 'None' | 'Warning' | 'Error'
Default: 'Error'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','TreatRealsInGeneratedCodeAs','Warning')
    makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','TreatRealsInGeneratedCodeAs','Warning')

See Also

Check for presence of unbalanced delays in generated HDL code

Specify whether to check for unbalanced delays in the generated HDL code.

Settings

Default: Error

None

Do not check for unbalanced delays in the generated HDL code.

Warning

Checks and warns of presence of unbalanced delays in the generated HDL code.

Error

Checks and generates an error if the generated HDL code uses unbalanced delays. If you are generating code for simulation purposes and not for synthesizing your design, you can change this setting to Warning or None.

Command-Line Information

Property: TreatBalanceDelaysOffAs
Type: character vector
Value: 'None' | 'Warning' | 'Error'
Default: 'Error'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Use hdlset_param to set the parameter on the model. Then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','TreatBalanceDelaysOffAs','Warning')
    makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','TreatBalanceDelaysOffAs','Warning')