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Multi-File Testbench and Simulation Library Path Parameters

This page describes configuration parameters that reside in the HDL Code Generation > Test Bench tab of the Configuration Parameters dialog box. Using the parameters in this tab, you can specify the simulation library path and whether to generate a multi-file testbench.

Multi-file test bench

Divide generated test bench into helper functions, data, and HDL test bench code files.

Description

You can use this setting to specify how you want to divide files that contain the test bench code, data, and helper functions.

The file names are derived from the name of the DUT, the Test bench name postfix property, and the Test bench data file name postfix property as:

DUTname_TestBenchPostfix_TestBenchDataPostfix

For example, if the DUT name is symmetric_fir, and the target language is VHDL®, the default test bench file names are:

  • symmetric_fir_tb.vhd: test bench code

  • symmetric_fir_tb_pkg.vhd: helper functions package

  • symmetric_fir_tb_data.vhd: data package

If the DUT name is symmetric_fir and the target language is Verilog®, the default test bench file names are:

  • symmetric_fir_tb.v: test bench code

  • symmetric_fir_tb_pkg.v: helper functions package

  • symmetric_fir_tb_data.v: test bench data

If the DUT name is symmetric_fir and the target language is SystemVerilog, the default test bench file names are:

  • symmetric_fir_tb.sv: test bench code

  • symmetric_fir_tb_pkg.sv: helper functions package

  • symmetric_fir_tb_data.sv: test bench data

Settings

Default: Off

On

Write three separate HDL files. There is a separate file for test bench code, helper functions, and test bench data.

Off

Write two separate HDL files. One file contains the HDL test bench code. The other file contains the helper functions package and test bench data.

Dependency

When this property is selected, Test bench data file name postfix is enabled.

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: MultifileTestBench
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, you can specify this parameter for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdltb function.

    makehdltb('sfir_fixed/symmetric_fir', ... 
            'MultifileTestBench', 'on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdltb.

    hdlset_param('sfir_fixed', 'MultifileTestBench', 'on')
makehdltb('sfir_fixed/symmetric_fir')

Simulation library path

Specify the path to your compiled Altera® or Xilinx® simulation libraries.

Settings

Default:''

Specify the path to the compiled Altera or Xilinx simulation libraries. Altera provides the simulation model files in \quartus\eda\sim_lib folder.

Dependency

This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.

Command-Line Information

Property: SimulationLibPath
Type: character vector
Default: ''

To set this property, use hdlset_param or makehdltb. To view the property value, use hdlget_param.

For example, if you want to set the path to the compiled Xilinx Simulation library, enter:

myDUT = gcb;

libpath = '/apps/Xilinx_ISE/XilinxISE-13.4/Linux/ISE_DS/ISE/vhdl/
   mti_se/6.6a/lin64/xilinxcorelib';

hdlset_param (myDUT, 'SimulationLibPath', libpath);

makehdltb(myDUT)