Properties for Controlling Script Generation

Enable or disable script generation and customize the names and content of generated script files by using the makehdl or makehdltb functions.

Enabling and Disabling Script Generation

The EDAScriptGeneration property controls the generation of script files. By default, EDAScriptGeneration is set on. To disable script generation, set EDAScriptGeneration to off, as in the following example.

makehdl('sfir_fixed/symmetric_fir','EDAScriptGeneration','off')

Customizing Script Names

When you generate HDL code, HDL Coder™ appends a postfix string to the model or subsystem name system in the generated script name.

When you generate test bench code, HDL Coder appends a postfix string to the test bench name testbench_tb.

The postfix string depends on the type of script (compilation, simulation, or synthesis) being generated. The default postfix strings are shown in the following table. For each type of script, you can define your own postfix using the associated property.

Script Type	Property	Default Value
Compilation	`HDLCompileFilePostfix`	`_compile.do`
Simulation	`HDLSimFilePostfix`	`_sim.do`
Synthesis	`HDLSynthFilePostfix`	Depends on the selected synthesis tool. See Choose synthesis tool.

The following command generates VHDL^® code for the subsystem system, specifying a custom postfix for the compilation script. The name of the generated compilation script will be system_test_compilation.do.

makehdl('mymodel/system', 'HDLCompileFilePostfix', '_test_compilation.do')

Customizing Script Code

Using the property name/property value pairs summarized in the following table, you can pass in customized format names as character vectors to makehdl or makehdltb. The properties are named according to the following conventions:

Properties that apply to the initialization (Init) phase are identified by the Init character vector in the property name.
Properties that apply to the command-per-file phase (Cmd) are identified by the Cmd character vector in the property name.
Properties that apply to the termination (Term) phase are identified by the Term character vector in the property name.

Property Name and Default	Description
Name: `HDLCompileInit` Default:`'vlib %s\n'`	Format name passed to `fprintf` to write the `Init` section of the compilation script. The implicit argument is the contents of the `VHDLLibraryName` property, which defaults to`'work'`. You can override the default `Init` string (`'vlib work\n'`) by changing the value of `VHDLLibraryName`.
Name: `HDLCompileVHDLCmd` Default: `'vcom %s %s\n'`	Format name passed to `fprintf` to write the `Cmd` section of the compilation script for VHDL files. The two implicit arguments are the contents of the `SimulatorFlags` property and the file name of the current entity or module. To omit the flags, set `SimulatorFlags` to `''` (the default).
Name: `HDLCompileVerilogCmd` Default: `'vlog %s %s\n'`	Format name passed to `fprintf` to write the `Cmd` section of the compilation script for Verilog^® files. The two implicit arguments are the contents of the `SimulatorFlags` property and the file name of the current entity or module. To omit the flags, set `SimulatorFlags` to `''` (the default).
Name:`HDLCompileTerm` Default:`''`	Format name passed to `fprintf` to write the termination portion of the compilation script.
Name: `HDLSimInit` Default: ['onbreak resume\n',... 'onerror resume\n']	Format name passed to `fprintf` to write the initialization section of the simulation script.
Name: `HDLSimCmd` Default: `'vsim -voptargs=+acc %s.%s\n'`	Format name passed to `fprintf` to write the simulation command. If your target language is VHDL, the first implicit argument is the value of the `VHDLLibraryName` property. If your target language is Verilog or SystemVerilog, the first implicit argument is `'work'`. The second implicit argument is the top-level module or entity name.
Name: `HDLSimViewWaveCmd` Default: `'add wave sim:%s\n'`	Format name passed to `fprintf` to write the simulation script waveform viewing command. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.
Name: `HDLSimTerm` Default: `'run -all\n'`	Format name passed to `fprintf` to write the `Term` portion of the simulation script. The string is a synthesis project creation command. The content of the string is specific to the selected synthesis tool. See Choose synthesis tool.
Name: `HDLSynthInit`	Format name passed to `fprintf` to write the `Init` section of the synthesis script. The content of the format name is specific to the selected synthesis tool. See Choose synthesis tool.
Name: `HDLSynthCmd`	Format name passed to `fprintf` to write the `Cmd` section of the synthesis script. The content of the format name is specific to the selected synthesis tool. See Choose synthesis tool.
Name: `HDLSynthTerm`	Format name passed to `fprintf` to write the `Term` section of the synthesis script. The content of the format name is specific to the selected synthesis tool. See Choose synthesis tool.

Examples

The following example specifies a custom VHDL library name for the Mentor Graphics^® ModelSim™ compilation script for code generated from the subsystem, system.

makehdl(system, 'VHDLLibraryName', 'mydesignlib')

The resultant script, system_compile.do, is:

vlib mydesignlib
vcom  system.vhd

The following example specifies that HDL Coder generate a Xilinx^® ISE synthesis file for the subsystem sfir_fixed/symmetric_fir.

 makehdl('sfir_fixed/symmetric_fir','HDLSynthTool', 'ISE')

The following listing shows the resultant script, symmetric_fir_ise.tcl.

set src_dir "./hdlsrc"
set prj_dir "synprj"
file mkdir ../$prj_dir
cd ../$prj_dir
project new symmetric_fir.ise
xfile add ../$src_dir/symmetric_fir.vhd
project set family Virtex4
project set device xc4vsx35
project set package ff668
project set speed -10
process run "Synthesize - XST"