Xilinx Zynq Platform
HDL Coder™ can generate an IP core, integrate it into your Vivado® project, and program the Zynq hardware. Using Embedded Coder®, you can generate and build the embedded software, and run it on the ARM® processor. See Hardware-Software Co-Design Workflow for SoC Platforms.
To deploy your design to the Zynq hardware, you must install the HDL Coder Support Package for Xilinx Zynq Platform. For installation information, see HDL Coder Supported Hardware.
Export Reference Design
|Define external IO interface for board object|
|Define external port interface for board object|
|Add and define internal IO interface between generated IP core and existing IP cores|
|Add and define AXI4 Master interface|
|Add and define AXI4 slave interface|
|Add AXI4-Stream interface|
|Add AXI4-Stream Video interface|
|Add clock and reset interface|
Board and Reference Design
|Specify Xilinx EDK MHS project file|
|Specify Xilinx Vivado exported block design Tcl file|
|Include IP modules from your IP repository folder in your custom reference design|
|Add and define custom parameters for your reference design|
|Check property values in reference design object|
|Check property values in board object|
|Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor|
|Specify whether to use an Embedded Coder support package|
|Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor|
|Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor|
|Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor|
|Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor|
|Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor|
- Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
- Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
- Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
- Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
- Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
- Debug IP Core Using FPGA Data Capture
This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.