Capture one buffer of data from HDL IP core running on FPGA
Alternatively, instead of using the
function to perform the operation defined by the System object™, you can call the System object with arguments, as if it were a function.
y = step(obj,x) and
y = obj(x)
perform equivalent operations.
captures live signal data from a design running on an FPGA. The FPGA must contain an HDL IP
core generated from the FPGA Data Capture Component Generator tool.
dataOut = step(
dataOut is a structure that contains a field for each signal
captured. Call the object function to specify the data type of each captured signal.
If at least one signal is enabled as part of the trigger condition, the HDL IP core waits for a match of the trigger condition and captures the data. If no signals are enabled as part of the trigger condition, the HDL IP core captures and returns the buffered data immediately. When you create the object, no trigger condition is set by default. Call the and object functions to configure a trigger condition.
dataOut — Captured data
Captured data, returned as a structure containing a field for the
Capture_Window signal, a field for the
Trigger_Position signal, and a field for each signal captured by
FPGA data capture. The captured signal field is a vector of Sample
depth values for each signal requested for data capture at generation time.
The fields of the structure have these signal names.
Capture_Window— This signal indicates the current capture window.
Trigger_Position— This signal indicates the position of the trigger detection clock cycle within a capture buffer.
All remaining fields — The signal names you specified at generation time.
Introduced in R2017a