HDL Verifier

R2026b

Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem

Description

The HDL Verifier app enables you to generate a SystemVerilog DPI component or an HDL Cosimulation block from a Simulink^® subsystem. The app then guides you through the workflow required to verify your HDL.

Select the HDL Verifier™ workflow on the left pane, under HDL Verifier Mode:

• HDL Cosimulation — Select this option to generate an HDL Cosimulation block. Follow the toolstrip sections to prepare and run an HDL cosimulation, and then view the results.

• DPI Component Generation — Select this option to generate a SystemVerilog DPI component. Follow the toolstrip sections to prepare and generate the component, and then view the results.

Open the HDL Verifier App

Simulink Toolstrip: On the Apps tab, under Code verification, validation, and test, click HDL Verifier. The HDL Verifier app opens in its own tab on the Simulink Toolstrip.

Examples

• Get Started with SystemVerilog DPI Component Generation
• Get Started with Simulink HDL Cosimulation

Version History

Introduced in R2020b

R2026b: FPGA features ported to other products

HDL Verifier no longer supports the following FPGA features:

• FPGA-in-the-loop

• FPGA data capture

• AXI manager

These features were previously provided through HDL Verifier support packages. This table lists the support package migrations and new product requirements.

Support Package Migration

Original Support Package (HDL Verifier)	New Support Package	Required Base Product
HDL Verifier Support Package for AMD FPGA and SoC Devices	SoC Blockset™ Support Package for AMD FPGA and SoC Devices	SoC Blockset for AMD
HDL Verifier Support Package for Intel® FPGA Boards	HDL Coder™ Support Package for Intel FPGA and SoC Devices	HDL Coder
HDL Verifier Support Package for Microchip FPGA Boards	HDL Coder Support Package for Microchip FPGA and SoC Devices	HDL Coder

R2024b: Simulink Toolstrip support for FPGA data capture workflow

To access FPGA data capture with Simulink, open the HDL Verifier app and select FPGA Data Capture (FDC) on the HDL Verifier Mode pane.

R2023b: DPI component generation requires ASIC Testbench

To access DPI and UVM component generation features, you must download the ASIC Testbench for HDL Verifier add-on.

R2023b: Simulink Toolstrip support for FPGA-in-the-loop workflow

To access FPGA-in-the-loop with Simulink, open the HDL Verifier app and select FPGA-in-the-Loop (FIL) on the HDL Verifier Mode pane.

R2021a: Simulink Toolstrip support for HDL cosimulation workflow

To access HDL cosimulation with Simulink, open the HDL Verifier app and select HDL Cosimulation on the HDL Verifier Mode pane.