This example shows the operation of two models of on load tap changer (OLTC) regulating transformer.
Gilbert Sybille (Hydro-Quebec)
A 25 kV distribution network consisting of three 30-km distribution feeders connected in parallel supplies power to a 36 MW /10 Mvar load (0.964 PF lagging) from a 120 kV, 1000 MVA system and a 120kV/25 kV OLTC regulating transformer. Reactive power compensation is provided at load bus by a 15 Mvar capacitor bank. The same circuit is duplicated in order to compare the performance of two different models of OLTC transformers:
Model 1 is a detailed model where all OLTC switches and transformer characteristics are represented. This model can be used with either continuous or discrete 'simulation type' modes of Powergui to get detailed wave shapes or with the phasor simulation method to observe variations of phasor voltages and currents. To simulate Model 1 in continuous or discrete you need to delete Model 2 from the example.
Model 2 is a simplified phasor model where the transformer and OLTC are simulated by current sources. This model can be used only with the phasor 'simulation type' mode of Powergui. It is much faster to execute and it should be the preferred model for transient stability studies, when several such devices are used in the same system.
Both OLTC transformer models implement a three-phase regulating transformer rated 47 MVA, 120 kV/25 kV, Wye/ Delta, with the OLTC connected on the high voltage side (120 kV). The OLTC transformers are used to regulate system voltage at 25 kV buses B2 and B4.
Voltage regulation is performed by varying the transformer turn ratio. This is obtained by connecting on each phase, a tapped winding (regulation winding) in series with each 120/sqrt(3) kV winding. Nine (9) OLTC switches allow selection of 8 different taps (tap positions 1 to 8, plus tap 0 which provides nominal 120kV/25 kV ratio). A reversing switch included in the OLTC allows reversing connections of the regulation winding so that it is connected either additive (positive tap positions) or subtractive (negative tap positions). For a fixed 25 kV secondary voltage, each tap provides a voltage correction of +/-0.01875 pu or +/-1.875% of nominal 120 kV voltage. Therefore, a total of 17 tap positions, including tap 0, allow a voltage variation from 0.85 pu (102 kV) to 1.15 pu (138 kV) by steps of 0.01875 pu (2.25 kV).
The positive-sequence voltages measured at buses B2 and B4 are provided as inputs to the voltage regulators (input 'Vmeas' of the transformer blocks). Open the two transformer block menus and look at their parameters. The voltage regulators are in service ('Voltage regulator' parameter = 'on'). The reference voltage is set to 1.04 pu. In order to start simulation with 25-KV voltages close to 1.04 pu at buses B2 and B4, the initial tap positions are set at -4, so that the transformers are boosting the voltage by a factor 1/(1-4*0.01875)=1.081.
The detailed model is built with a fixed number of taps (8). Note that the phasor model provides more flexibility as it allows selection of primary and secondary winding connections (wye or Delta) as well as changing the number of taps and using the OLTC either on primary or secondary side.
You can also use 'Edit/Look under mask' to see how the transformer models are built. The detailed model is built from three Multi-Winding Transformer blocks and three OLTC subsystems which contain switches performing tap selection and reversal of the regulation winding. The tap transition is performed by temporarily short-circuiting two adjacent transformer taps through resistors (5 ohm resistances and 60 ms transition time as specified in the block menu). The phasor model is built with current sources emulating the transformer impedance which depends on winding resistances, leakage reactances and tap position. Both models use a voltage regulator that generates pulses at the 'Up' or 'Down' outputs and orders a tap change either in the positive or negative direction. The voltage regulation depends on the specified dead band (DB = two times the voltage step or 0.0375 pu). This means that the maximum voltage error at buses B2 and B4 should be 0.01875 pu. As long as the maximum tap number is not reached (-8 or +8), voltage should stay in the range : ( Vref-DB/2< V<1.04+DB/2 ) = (1.021< V< 1.059).
As tap selection is a relatively slow mechanical process (4 sec per tap as specified in the 'Tap selection time' parameter of the block menus), the simulation Stop time is set to 2 minutes (120 s). The Three-Phase Programmable Voltage Source is used to vary the 120 kV system voltage in order to observe the OLTC performance. Initially, the source is generating its nominal voltage. Then, voltage is successively decreased (0.95 pu at t = 10 s) and increased (1.10 pu at t = 50 s).
Start the simulation and observe OLTC operation on the Scope.
Trace 1 shows the tap position.
Trace 2 shows a superposition of positive-sequence voltages at 120 kV bus B1 (yellow ), at 25 kV bus B2 (magenta) and bus B4 (cyan).
Traces 3 and 4 show the active and reactive powers measured on 120 kV side (buses B1 and B3).
When simulation starts the OLTCs are at position -4 and the resulting voltage at bus B2 and B4 is 1.038 pu. At t=10 s, the source internal voltage is suddenly lowered to 0.95 pu , so that the 25 kV voltages drop to 0.986 pu, outside of the permitted voltage range (1.021< V<1.059). The voltage regulator then orders further voltage boosting and the OLTC stabilizes at tap=-6 (V=1.025 pu) At t=50 s, the source internal voltage is suddenly increased to 1.10 pu , so that the 25 kV voltages now reach to 1.19 pu. The voltage regulator then starts to decrease voltage by moving taps in the upward direction and the OLTCs stabilize at tap=+1 (V=1.043 pu).
Simulation with phasor model only
In order to appreciate the gain in simulation speed provided by the phasor model, delete the detailed transformer model and replace it with a duplicate of the phasor model. Restart simulation. The model runs approximately 2.5 times faster, mainly because the OLTC switches of the detailed model are not simulated.
Note: The voltage glitches observed with the phasor model when the source voltage is stepped down (t= 10s) and up (t=50 s) can be ignored. They are caused by the first order transfer functions (one cycle time constant) which are used inside the model to break algebraic loops.