Design Range Checks

Check for specified minimum and maximum signal values

Functions

`sldvextract`	Extract subsystem or subchart contents into new model for analysis
`sldvoptions`	Create design verification options object
`sldvrun`	Analyze model
`sldvreport`	Generate Simulink Design Verifier report
`sldvmakeharness`	Generate harness model

Explains the design error detection analysis option.

Explains the concepts of design ranges and derived ranges with regard to design error detection.

Describes the recommended workflow for detecting design errors.

Describes how to analyze the model to verify that specified design minimum and maximum values are honored.

Specify analysis options and configure Simulink^® Design Verifier™ output.

Specify options that control how Simulink Design Verifier detects runtime errors in the models it analyzes.

Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.

Review analysis results in the Simulink Design Verifier Results Summary window.