Input Range Constraints
- Specify Input Ranges on Simulink and Stateflow Elements
Describes how the analysis handles minimum and maximum values on Simulink® and Stateflow® elements.
- Review Analysis Results
Review analysis results in the Simulink Design Verifier™ Results Summary window.
- Check for Specified Minimum and Maximum Value Violations
Describes how to analyze the model to verify that specified design minimum and maximum values are honored.
- Minimum and Maximum Input Constraints
An overview of how the Simulink Design Verifier analysis considers specified input minimum and maximum values.
- Specification of Input Ranges in sldvData Fields
sldvDatafields for minimum and maximum input values.
- Using Specified Input Minimum and Maximum Values as Constraints
This example shows how to use input port minimum and maximum values as analysis constraints by Simulink Design Verifier during both test generation and property proving.
- Specify Signal Ranges
Specify the minimum and maximum value that a signal can attain during simulation. Fully specify your design and optimize data types and the generated code by specifying the minimum and maximum value that a signal can attain during simulation.
- Specify Parameter Configuration for Structure or Bus Parameters
This example describes how to generate tests that constrain the values for the structures and bus signals in a model.