This example shows how to model an algorithm partitioned between hardware and software. The hardware IP is implemented in FPGA fabric, and triggers a software task implemented in the embedded processor. Design, simulate, and implement a complete design on SoC hardware.
Supported hardware platforms:
Xilinx® Zynq® ZC706 evaluation kit
Xilinx Zynq UltraScale™+ MPSoC ZCU102 Evaluation Kit
Xilinx Zynq UltraScale™+ RFSoC ZCU111 Evaluation Kit
ZedBoard™ Zynq-7000 Development Board
Altera® Cyclone® V SoC development kit
Altera Arria® 10 SoC development kit
Many System-on-Chip (SoC) applications require the hardware device to trigger an asynchronous task on the processor. This functionality can be useful when implementing low-latency control loops that span between the hardware and software. It is also useful in handling urgent hardware requests by the software. For such designs, the hardware device raises an interrupt request to the interrupt controller to signify that data is ready for action by the software task on the processor.
This example includes two hardware IP cores in the FPGA. These IP cores generate the interrupt signals asynchronously. The interrupts trigger two separate tasks on the processor, one for each hardware IP core. The processor tasks access the hardware devices by reading or writing registers.
The top model sw_hw_interrupt_top includes the FPGA model sw_hw_interrupt_fpga and processor model sw_hw_interrupt_proc as model references. The top model also includes the Interrupt Channel and Register Channel blocks to model data transfers from the FPGA to the Processor.
The FPGA model implements two IP cores that generate interrupts based on incrementing 32 bit-counter values. The first IP core generates an interrupt when either the 16th or the 18th bit of the counter value changes from 0 to 1. The second IP core generates an interrupt when either the 14th or 16th bit of the counter value changes from 0 to 1. The counter value at the time of generating the interrupt is registered and transferred to the processor using the Register Channel block. The processor model implements two software tasks, one for each IP core, that read the counter value, previously registered by the FPGA.
Simulate the system for 0.03 seconds and open the Scope block on the top model to visualize the counter values as they are read by the processor.
Next, on the Simulation tab, click Data Inspector to view the timing of various events triggered by interrupts. Add interrupt1 and interruptTask1 signals in the top view, and add interrupt2 and interruptTask2 signals in the bottom view. The simulation plot shows that everytime an interrupt is triggered, the corresponding task is executed. At time 0.01802 seconds, interrupt2 is raised and takes 100 microseconds to process by the Interrupt Channel block and to trigger the corresponding interruptTask2, which takes 500 microseconds to run.
At time 0.01966 seconds, interrupt1 & interrupt2 are raised at the same time, and they are serviced by the processor based on their relative priority. Since interrupt1 is connected first at the input ports of the Interrupt Channel block, it has a higher priority than interrupt2. interruptTask2 waits to be executed while interruptTask1 is still executing due to the higher priority of interrupt1.
These products are required for this section:
SoC Blockset Support Package for Xilinx Devices, or SoC Blockset Support Package for Intel Devices
For more information about support packages, see SoC Blockset Supported Hardware.
To implement the model on a supported SoC board use the SoC Builder tool. By default, the model will be implemented on ZedBoard as it is configured with that board. To open SoC Builder click, 'Configure, Build, & Deploy' button in the toolstrip and follow these steps:
Select Build Model on the Setup screen. Click Next.
Click Next on the Review Task Map screen.
On Review Memory Map screen, click View/Edit Memory Map to view the memory map. Click Next.
Specify the project folder on the Select Project Folder screen. Click Next.
Select Build, load for external mode on the Select Build Action screen. Click Next.
On Validate Model screen, click Validate to check the compatibility of model for implementation. Click Next.
On Build Model screen, click Build to begin building of the model. An external shell opens when FPGA synthesis begins. Click Next.
Click Test Connection on the Connect Hardware screen to test the connectivity of the host computer with SoC board. Click Next to go to the Run Application screen.
The FPGA synthesis may take more than 30 minutes to complete. To save time, you may want to use the provided pre-generated bitstream by following these steps:
Close the external shell to terminate synthesis.
Copy pregenerated bitstream to your project folder by running this
copyfile command below
Click Load and Run to load the pregenerated bitstream and run the model on SoC board
copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot,'toolbox','soc',... 'supportpackages','xilinxsoc','xilinxsocexamples','bitstreams',... 'soc_hwsw_interrupt_top-zedboard.bit'), './soc_prj');
After loading the bitstream, run the generated software model soc_hwsw_interrupt_sw in external mode. From the model toolbar, open the Data Inspector and add interruptTask1 in the top view and interruptTask2 into the bottom view. Observe that everytime an interrupt is triggered the corresponding task is executed.
Implementation on other boards: To implement the model on a supported board other than ZedBoard, first configure the model to the supported board, and then set the example parameters as below.
On the Hardware tab, click Hardware Settings to open the Configuration Parameters window.
On the Hardware Implementation tab, select your board from Hardware board on the top and processor model.
On the Target hardware resources > FPGA design (top level) tab enable Include MATLAB as AXI Master IP for host-based interaction and set IP core clock frequency (MHz) to 10 MHz.
Next, click Configure, Build, & Deploy on the toolstrip to open SoC Builder and follow the steps as previously stated for ZedBoard above. Modify the
copyfile command to match the bitstream corresponding to your board. In case of Altera Arria® 10 SoC development kit and Altera Cyclone® V SoC development kit use below
copyfile command corresponding to your board. In case of Altera Arria® 10 SoC development kit, copy '.periph.rbf' and '.core.rbf' files.
copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot,'toolbox','soc',... 'supportpackages','intelsoc','intelsocexamples','bitstreams',... 'soc_hwsw_interrupt_top-c5soc.rbf'), './soc_prj');
The following are the available pre-generated bitstream files:
In summary, this example showed how interrupts from the FPGA trigger actions in the processor. You modeled the behavior using SoC Blockset, and went through the workflow required to implement it on an SoC device.