Transmit and Receive Tone Using OTAVA DTRX2 mmWave Radio Card

This example uses:

This example shows how to integrate an OTAVA DTRX2 mmWave radio card with a Xilinx® Zynq® UltraScale+™ RFSoC ZCU208 Evaluation Kit by using SoC Blockset™. In this example, you design, simulate, and deploy a system that generates a sinusoidal tone from an FPGA and transmit the tone in mmWave band through mmWave radio card by using the RF Data Converter (RFDC) and OTAVA DTRX2 blocks. The system then receives the data back into the FPGA by using the OTAVA DTRX2 and RFDC blocks and visualizes the received tone by using an embedded processor.

Supported Hardware Platforms

Xilinx Zynq UltraScale+ RFSoC ZCU208 evaluation kit and OTAVA DTRX2 mmWave radio card with lowpass filter and 27.5 GHz to 31 GHz nine-section bandpass filter.

Supported Tools

SoC Blockset Support Package for AMD® FPGA and SoC Devices

Avnet RFSoC Explorer V2.3

Design Task and System Specification

Consider a wireless application that transmits and receives a signal in the mmWave band on the Xilinx RFSoC device. In this example, the design task is to generate a sinusoidal tone from the FPGA, configure the RFDC and OTAVA DTRX2 blocks for a mmWave band transceiver, and receive the data back into the FPGA on ZCU208 evaluation kit with these system specifications.

System Specifications

RF Carrier Frequency = 27.5 GHz
Receive Intermediate Frequency = 4.3 GHz
Transmit Intermediate Frequency = 3.7 GHz

Design Using SoC Blockset

Create an SoC model soc_mmWave_datacapture_top model as the top model and set Hardware Board to Xilinx Zynq Ultrascale+ RFSoC ZCU208 Evaluation Kit. This model includes the soc_mmWave_datacapture_fpga FPGA model and the soc_mmWave_datacapture_proc processor model, which are instantiated as model references. The top model also includes the AXI4-Stream to Software block, which shares the external memory between the FPGA and the processor.

open_system('soc_mmWave_datacapture_top')

close_system('soc_mmWave_datacapture_top')

OTAVA DTRX2 Configuration

The OTAVA DTRX2 mmWave radio card is an RF front-end card in the mmWave frequency band (19 to 31 GHz). Integrate this card with the ZCU208 RFSoC evaluation board to build the complete system for wireless applications in the mmWave band. It has two transmit and receive channels. To configure the RF card, use OTAVA DTRX2 block. The block provides RF front-end control path interface for the configuration of the transmit and receive channels of the OTAVA DTRX2 mmWave radio card.

To meet the system requirements, open the OTAVA DTRX2 block and follow these steps:

For transmit and receive channels, set Center frequency (GHZ) to 27.5.
For transmit channel, set Intermediate frequency (GHz) to 4.3 and for receive channel, set Intermediate frequency (GHz) to 3.7.
For transmit and receive channels, set the IF and RF attenuation parameters to their default values.

RF Data Converter Configuration

An RFSoC device has its RF data converter connected to the programmable logic. To configure the ADC and DAC settings, use the RFDC block. The block provides an interface to the Xilinx RF Data Converter IP in Simulink for modeling a wireless system destined for implementation on Xilinx RFSoC device.

To meet the system requirements, the data rate for DAC is 6144 MSPS and ADC is 4915.2 MSPS, you must choose the values of the Interpolation mode, Decimation mode, and Samples per clock cycle parameters such that the effective clock cycle (sample rate) for the wireless algorithm FPGA is in the desirable range. The parameter values are displayed on the block under Stream clock frequency after you click Apply.

For this example, in the DAC tab, set Interpolation mode to 10 and Samples per clock cycle to 4. In the ADC tab, set Decimation mode to 8 and Samples per clock cycle to 4. These values imply a Stream clock frequency value of 6144/(10*4) = 153.6 MHz.

To meet the system specification of transmit IF specification, on the DAC tab, set NCO frequency (GHz) to 4.3. To meet the receive IF specification, on the ADC tab, set NCO frequency (GHz) to -3.7.

Hardware Logic Design

The soc_ddr4datacapture_fpga FPGA model contains two subsystems, DAC Tone Generation, which is connected to the DAC portion of the RFDC block, and ADC Capture subsystem, which is connected to the ADC portion.

open_system('soc_mmWave_datacapture_fpga')

close_system('soc_mmWave_datacapture_fpga')

The DAC Tone Generation subsystem generates four consecutive samples of the sinusoidal waveform in parallel by using four HDL Optimized NCO blocks. Each HDL Optimized NCO block has a different offset. The four samples comprise 64 bits of data and have the same width as AXI-Stream data.

The ADC Capture subsystem uses a trigger and capture logic to capture ADC RF samples and sends the data to the processor to display the captured signal. The triggerFreq register from the processor controls the trigger and capture logic.

Processor Logic Design

The processor logic contains an event-based task driven by the arrival of data from the FPGA through the DDR memory. The processor algorithm task is denoted as dataTask in the Task Manager block and is specified as event driven. The Task Manager block schedules data asynchronously by means of the buffer ready event rdEvent in the memory, denoting the arrival of a frame of data from the FPGA. The algorithm itself is modeled under the Processor Algorithm Wrapper subsystem in the processor model soc_mmWave_datacapture_proc and connected to the Task Manager block at the top level. To operate on the data received as a frame of four packed samples with the uint64 data type, you must first unpack and restore the signedness of the data. The output of the Processor Algorithm Wrapper subsystem is then connected to the Spectrum and Time scope for visualization. In a separate Initialize Function subsystem, various registers on the FPGA subsystems are initialized with their default values.

open_system('soc_mmWave_datacapture_proc')

close_system('soc_mmWave_datacapture_proc')

Simulate

Run the model. The sinusoidal tone generated from the FPGA sends to the OTAVA DTRX2 block through RFDC. The waveform loops back from the FPGA to the processor through the OTAVA DTRX2 and RFDC blocks, and the ADC Capture subsystem in FPGA for capturing the waveform. In the processor system, the waveform is visualized in the frequency domain using a Spectrum Analyzer block named ADC Captured Signal. The data is observed on the spectrum scope with a substantial delay after the start of the simulation. This delay is because of the delay in the availability of the first frame of data through the DDR4 to the scope, which is due to the length of the loop back data path. The transmitted and received signals have a tone of 15 MHz.

Implement and Run on Hardware

Hardware Setup

Connect the OTAVA DTRX2 mmWave radio card to the ZCU208 evaluation board at the RFMC interface. Connect the SMA connector on the OTAVA DTRX2 mmWave radio card to complete the loopback between the Tx Channel1 (J3) and Rx Channel1 (J10). Connect DC power supply to the OTAVA DTRX2 mmWave radio card and set the voltage to 12 V and maximum current limit to 2 A.

To implement the model on a supported SoC board, use the SoC Builder tool. Ensure that the Hardware Board is set to Xilinx Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit in the System on Chip tab of the Simulink toolstrip.

To open SoC Builder, click Configure, Build, & Deploy. After the SoC Builder tool opens, follow these steps.

On the Setup screen, select Build model. Click Next.
On the Select Build Action screen, select Build and load for external mode. Click Next.
On the Select Project Folder screen, specify the project folder. Click Next.
On the Review Hardware Mapping screen, click Next.
On the Review Memory Map screen, to view the memory map, click View/Edit. Click Next.
On the Validate Model screen, to check the compatibility of the model for implementation, click Validate. Click Next.
On the Build Model screen, to begin building the model, click Build. An external shell opens when FPGA synthesis begins. Click Next.
On the Connect Hardware screen, to test the connectivity of the host computer with the SoC board, click Test Connection. Click Next.

The FPGA synthesis can take more than 30 minutes to complete. To save time, you can use the provided pregenerated bitstream by following these steps.

Close the external shell to terminate the FPGA synthesis.
Copy the pregenerated bitstream to your project folder by entering this command at the MATLAB command prompt.

copyfile(fullfile(matlabshared.supportpkg.getSupportPackageRoot,'toolbox','soc','supportpackages','xilinxsoc','xilinxsocexamples','bitstreams','soc_mmWave_datacapture_top-XilinxZynqUltraScale_RFSoCZCU208EvaluationKit.bit'),'./soc_prj');

Click Load and Run button to load the pregenerated bitstream and run the model on the SoC board.

After the bit file is loaded, open the generated software model.

Run the model in external mode by clicking Monitor & Tune. You can control the configuration from the Simulink model. Copy the spectrum analyzer from the top model and, connect it to the rate transition block as this figure shows, and run the model. The spectrum analyzer displays the received signal waveform with a frequency of 15 MHz.

Summary

In this example you design the data and control paths to integrate an OTAVA DTRX2 mmWave radio card on the Xilinx ZCU208 RFSoC evaluation kit. You design a system that generates a sinusoidal waveform with multiple samples per clock cycle and configure the RFDC and OTAVA DTRX2 blocks to transmit in the mmWave frequency. You also design the data path to receive the transmitted samples back into the device and verify the waveforms by simulation. You target the design hardware and verify the tone loopback signal in the mmWave RF band. You can use this example as a reference for designing your application that transmits and receives a signal in the mmWave band and for over-the-air testing in the mmWave band.