Access FPGA External Memory Using MATLAB as AXI Master

This example shows how to use MATLAB as AXI Master to access the external DDR memories connected to the FPGA. In the FPGA, there is a Xilinx DDR memory controller instantiated for accessing the DDR memories. This memory controller provides an AXI4 slave interface for read and write operations by other components in the FPGA. The MATLAB as AXI Master feature provides an AXI master component that can be used to access any AXI slave IPs in the FPGA. In this example, we demonstrate how to integrate this AXI master into a Xilinx Vivado project, and read/write to the DDR memory using MATLAB.


  • Xilinx® Vivado(TM)of compatible version

  • Artix-7 35T Arty FPGA Evaluation Kit

  • HDL Verifier™ Support Package for Xilinx FPGA Boards

Set Up

Step 1: Set up FPGA board Make sure that the Arty board is connected to the host computer via USB JTAG cable.

Step 2: Prepare example in MATLAB Set up the Xilinx Vivado tool path. Use your own Xilinx Vivado installation path when executing the command. For example:

>> hdlsetuptoolpath('ToolName', 'Xilinx Vivado', 'ToolPath', 'C:\Xilinx\Vivado\2016.2\bin\vivado.bat');

Create a folder outside the scope of your MATLAB installation folder into which you can copy the example files. The folder must be writable. This example assumes that the folder is located at C:\MyTests.

Start MATLAB and set the current directory in MATLAB to the folder you just created. For example:

>> cd C:\MyTests

Copy the example files into current directory by executing this command in MATLAB

>> copyXilinxFPGAExampleFiles('aximaster')

Create a Vivado project for this example. This project contains the IP Integrator block diagram as well as constraint file that we created for this example.

>> system('vivado -mode batch -source createproject.tcl')

This command takes about one minute to finish. When it is done, a Vivado project named "arty.xpr" exists in your current directory.

Step 3: Configure Vivado project with Vivado IP To use the MATLAB as AXI Master IP inside Vivado IP Integrator, add the folder that contains the IP to the Vivado project's IP repository path setting. You can add the path to the project from MATLAB with this command :

>> setupAXIMasterForVivado arty.xpr

Next, open the generated Vivado project in GUI mode. You can double-click the project in a file browser, or execute this command in MATLAB

>> system('vivado arty.xpr &')

Step 4: Add MATLAB as AXI Master IP to the FPGA design

In the Vivado GUI, open the block diagram design file You can find it in the source file sub-window.

Set the address of mig_7series_0 (memory controller) to 0x0000_0000 in the address editor as shown:

Alternatively, you can complete these setup steps by executing tcl commands in Vivado.

open_bd_design {arty.srcs/sources_1/bd/design_1/} create_bd_cell -type ip -vlnv hdlverifier_axi_master_0 connect_bd_intf_net [get_bd_intf_pins hdlverifier_axi_master_0/axi4m] [get_bd_intf_pins mig_7series_0/S_AXI] connect_bd_net [get_bd_pins hdlverifier_axi_master_0/aclk] [get_bd_pins mig_7series_0/ui_clk] connect_bd_net [get_bd_pins hdlverifier_axi_master_0/aresetn] [get_bd_pins util_vector_logic_0/Res] regenerate_bd_layout assign_bd_address [get_bd_addr_segs {mig_7series _0/memmap/memaddr }] set_property offset 0x00000000 [get_bd_addr_segs {hdlverifier_axi_master_0/axi4m/SEG_mig_7series_0_memaddr}]

Step 5: Generate FPGA programming file and program FPGA Click "Generate Bitstream" on the left of Vivado window to generate the FPGA programming file. Vivado might prompt you to save the project before moving forward. It takes about 5 to 10 minutes for Vivado to generate the bitstream file.

After generating the bitstream, program the FPGA in MATLAB using the following command:

>> filProgramFPGA('Xilinx Vivado','arty.runs\impl_1\design_1.bit',1)

Read and Write Operations to the FPGA

After programming the FPGA, you can read and write into the AXI slaves connected to the MATLAB as AXI Master IP. In this example, the data will be written to the DDR memory connected to the FPGA, and retrieved back into MATLAB.

First, you need to create the AXI master object in MATLAB

>> h = aximaster('Xilinx', 'TckFrequency', 66)

Here, we set the maximum JTAG clock (Tck) frequency to 66MHz, which is the maximum allowed number for the Artix-7 device on ARTY FPGA board. Then you can run the following two commands to write a single word (32bit) of value 100 into DDR memory at address 0 and read it back by using the AXI master object :

>> writememory(h, 0,100)
>> readmemory(h, 0,1)