ADC To Vector

Convert concatenated 16-bit ADC input samples to vector outputs

Since R2020b

Add-On Required: This feature requires the SoC Blockset Support Package for Xilinx Devices add-on.

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Libraries:
SoC Blockset Support Package for Xilinx Devices / RFSoC / ZCU111
SoC Blockset Support Package for Xilinx Devices / RFSoC / ZCU208
SoC Blockset Support Package for Xilinx Devices / RFSoC / ZCU216

Description

The ADC To Vector block converts the concatenated 16-bit analog-to-digital converter (ADC) input samples to vector outputs.

The block accepts 16-bit samples packed into N x 16 bits through the adcData input port and outputs a vector of N samples through the vectorData output port. N is the number of samples per clock cycle.

Examples

Transmit and Receive Tone Using Fixed Reference Design Workflow on RFSoC Device

Design and implement hardware algorithm using RFSoC support for fixed reference design workflow.

Open Script

Ports

Input

adcData — ADC data samples

scalar

ADC data samples, specified as a scalar. The size of this input must be N x 16 bits, where N is the number of samples per clock cycle set by the Samples per clock parameter.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

Output

vectorData — ADC data samples in vector form

vector

ADC data samples, returned as a vector. The block returns the data as an N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock parameter.

For example, consider the case where N = 2 and the input to the adcData port is of size 32 bits. In this case, the block returns vector [S₀, S₁], where S₀ is a 16-bit value sliced from 0 to 15 bits of input data from the adcData port, and S₁ is a 16-bit value sliced from 16 to 31 bits of input data from the adcData port.

Data Types: int16 | uint16

Parameters

Samples per clock — Number of samples per clock cycle

4 (default) | integer from 1 to 16

Specify the number of samples per clock cycle as an integer from 1 to 16. This parameter sets the required bit width of the input samples and sets the output vector size.

Output data type — Output data type

fixdt(1,16,0) (default) | int16 | uint16

Specify the output data type as a signed or unsigned fixed point or an integer data type. For more information on how to specify output data type, see Specify Data Types Using Data Type Assistant.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2020b