RF Data Converter

Provide RF data path interface to hardware logic

Since R2020a

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Libraries:
SoC Blockset Support Package for Xilinx Devices / SDR / RFDataConverter

Description

The RF Data Converter block provides an RF data path interface to the hardware logic.

The block accepts 16-bit samples packed into N x 16 bits through dacxData ports and outputs a vector of N samples through dacx ports. The block accepts a vector of N samples through adcx ports and outputs 16-bit samples packed into N x 16 bits through adcxData ports based on the N value. N is the number of samples per clock cycle, and the possible values of x range from 1 to m, where m is the maximum number of analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) available on the selected hardware board. The block supports a maximum of 16 ADC and 16 DAC data paths connecting to the hardware logic.

In generation, the SoC Builder tool maps the block parameters to the RF Data Converter IP on the hardware.

The block supports Gen 1, Gen 2, and Gen 3 Zynq^® UltraScale+™ RFSoC devices. For a full list of supported devices, see Supported Third-Party Tools and Hardware. For specific Zynq UltraScale+ RFSoC device information, see Zynq UltraScale+ RFSoC Product Information from the Xilinx^® website.

Examples

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design

Design a data path for a Xilinx® RFSoC device by using SoC Blockset®. You will design and simulate a system that generates a sinusoidal tone from an FPGA and transmit the tone across multiple RF channels by using the RF Data Converter (RFDC) block. The system will then receive the data back into the FPGA by using the RFDC block and visualizes the received tone for one channel at a time by using an embedded processor.

Open Example

Transmit and Receive Tone Using Xilinx RFSoC Device - Part 2 Deployment

Implement and verify a design on Xilinx® RFSoC device using SoC Blockset™. You deploy a system on Xilinx RFSoC evaluation kits that generates a sinusoidal tone from an FPGA, transmits it across multiple RF channels, and receives it back into the device to complete the loopback. For modeling and simulation of the system, see the Transmit and Receive Tone Using Xilinx RFSoC Device - Part 1 System Design example.

Open Example

5G NR MIB Recovery Using Xilinx RFSoC Device

Simulate and deploy a 5G NR MIB Recovery algorithm in Simulink® using an SoC Blockset™ implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can recover, demodulate a primary synchronization signal (PSS) and secondary synchronization signal (SSS) and decodes MIB report from the 5G NR waveforms and simulate the Cell Search control algorithm sequence running on a processor while interacting with the Cell Search hardware algorithm. In simulation, you can fine tune and verify the controller in the processor and hardware algorithm in the FPGA at a system level before implementing them on the hardware.

Open Example

OFDM Transmit and Receive Using Xilinx RFSoC Device

Simulate and deploy an orthogonal frequency division multiplexing (OFDM) transmit and receive algorithm in Simulink® using an SoC Blockset™ implementation targeted on a Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation board. Using this example, you can integrate HDL OFDM Transmitter (Wireless HDL Toolbox) and HDL OFDM Receiver (Wireless HDL Toolbox) examples into the SoC Blockset implementation.

Open Example

Pulse-Doppler Radar Using Xilinx RFSoC Device

Build, simulate, and deploy a pulse-Doppler radar system in Simulink® using an SoC Blockset™ implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC evaluation kit. Using this example, you can detect and estimate the range and velocity of moving targets. The range-Doppler processing is partitioned across a field-programmable gate array (FPGA) and a processor. The range processing is handled in the FPGA and the Doppler processing is handled in the processor. The example also implements a radar target emulator to evaluate the performance of the radar.

Open Example

Frequency Hopping Using Xilinx RFSoC Device

Design and implement frequency hopping algorithm using Xilinx RF Data Converter numerically controlled oscillator (NCO) real time ports.

Open Example

Ports

Input

adcx — ADC input data

column vector

ADC input data, specified as a column vector.

x indicates the number of adc ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adc ports. For example, if RF interface is set to ADC & DAC 2x2 RF Interface, the block has ports adc1 and adc2, that is, one input port per ADC channel interface.

Valid values for this port are based on the Digital interface parameter value.

• If you set the Digital interface parameter to Real, specify this value as an N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

  Use this option to specify real-valued data. For example, consider N equal to 2 and data containing two real values D₀ and D₁. In this case, specify this port value as a vector of the form [D₀ D₁].

• If you set the Digital interface parameter to I/Q, specify this value as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

  Use this option to specify complex-valued data. For example, consider N equal to 2 and data containing two complex values with real parts I₀ and I₁ and imaginary parts Q₀ and Q₁, respectively. In this case, specify this port value as a vector of the form [I₀ Q₀ I₁ Q₁].

Data Types: int16 | uint16

dacxData — DAC input data

scalar | column vector

DAC input data, specified as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of dacxData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

dacxIData — Real part of DAC input

scalar | column vector

Real part of DAC input, specified as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of dacxIData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

dacxQData — Imaginary part of DAC input

scalar | column vector

Imaginary part of DAC input, specified as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of dacxQData ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxQData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: int16 | int32 | int64 | uint16 | uint32 | uint64 | fixed point

dacxValid — Indication of valid DAC input data

Boolean scalar

Indication of valid DAC input data, specified as a scalar.

A value of 1 indicates when the data on the dacxData port is valid or when the data on the dacxIData and dacxQData ports is valid.

x indicates the number of dacxValid ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxValid ports.

Data Types: Boolean

adcxRealTimeCtrlIn — ADC real-time control input

bus

ADC real-time control input, specified as a bus.

x indicates the number of adcxRealTimeCtrlIn ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxRealTimeCtrlIn ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has two input ports, one per ADC channel interface.

Dependencies

To enable this port, select Real-time ports or Real-time NCO ports on the Advanced tab.

Data Types: DUT2RFDCRealTimeCtrlBusObj

adcTileyNCOUpdateReq — ADC NCO update request

Boolean scalar

ADC-numerically controlled oscillator (NCO) update request, specified as a Boolean scalar. To request an update of the ADC NCO settings, set this input signal to High.

y indicates the number of adcTileyNCOUpdateReq ports and ranges from 1 to k, where k is the maximum number of ADC tiles available on the selected hardware board. The RF interface parameter sets the number of adcTileyNCOUpdateReq ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has one input port, one per ADC tile.

Dependencies

To enable this port, select Real-time NCO ports under the ADC section on the Advanced tab.

Data Types: Boolean

dacxRealTimeCtrlIn — DAC real-time control input

bus

DAC real-time control input, specified as a bus.

x indicates the number of dacxRealTimeCtrlIn ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacxRealTimeCtrlIn ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has two input ports, one per DAC channel interface.

Dependencies

To enable this port, select Real-time NCO ports under the DAC section on the Advanced tab.

Data Types: DUT2RFDCRealTimeCtrlBusObj

dacTileyNCOUpdateReq — DAC NCO update request

Boolean scalar

DAC NCO update request, specified as a Boolean scalar. To request an update of the DAC NCO settings, set this input signal to High.

y indicates the number of dacTileyNCOUpdateReq ports and ranges from 1 to k, where k is the maximum number of DAC tiles available on the selected hardware board. The RF interface parameter sets the number of dacTileyNCOUpdateReq ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has one input port, one per DAC tile.

Dependencies

To enable this port, select Real-time NCO ports under the DAC section on the Advanced tab.

Data Types: Boolean

dacTile1SysrefGating — Synchronous clock gating for MTS mode

Boolean scalar

Synchronous clock gating for the multi-tile synchronization (MTS) mode, specified as a Boolean scalar. To disable the DAC tile from the Sysref clock signal, set this input signal to High.

Dependencies

To enable this port, select Multi tile sync under the Common Parameters section and select Real-time NCO ports under the DAC section on the Advanced tab.

Data Types: Boolean

dacTile1SysrefReEnable — Synchronous clock re-enabling for MTS mode

Boolean scalar

Synchronous clock re-enabling for the MTS mode, specified as a Boolean scalar. To re-enable the Sysref clock signal, set this input signal to High.

Dependencies

To enable this port, select Multi tile sync under the Common Parameters section and select Real-time NCO ports under the DAC section on the Advanced tab.

Data Types: Boolean

Output

dacx — DAC output data

column vector

DAC output data, returned as a column vector.

• If you set the Digital interface parameter to Real, the block returns outputs as a N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

  For example, consider N equal to 2 and input to the dac1Data port is of size 32 bits. In this case, this port returns a vector [S₀ S₁], where S₀ is a16-bit value sliced from 0 to 15 bits of input data on the dac1Data port and S₁ is a 16-bit value sliced from 16 to 31 bits of input data on the dac1Data port.

• If you set the Digital interface parameter to I/Q, the block returns outputs as a 2N-element column vector, where N is the number of samples per clock cycle set by the Samples per clock cycle parameter.

  For example, consider N equal to 2 and inputs to dac1IData and dac1QData ports are of size 32 bits. In this case, this port returns a vector [I₀ Q₀ I₁ Q₁], where I₀ is a16-bit value sliced from 0 to 15 bits of input data on the dac1IData port and I₁ is a 16-bit value sliced from 16 to 31 bits of input data on the dac1IData port and Q₀ is a16-bit value sliced from 0 to 15 bits of input data on the dac1QData port and Q₁ is a 16-bit value sliced from 16 to 31 bits of input data on the dac1QData port.

x indicates the number of dacx ports and ranges from 1 to m, where m is the maximum number of DACs available on the selected hardware board. The RF interface parameter sets the number of dacx ports.

Data Types: int16

adcxData — ADC output data

scalar | column vector

ADC output data, returned as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of adcxData ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to Real.

Data Types: uint16 | uint32 | uint64 | fixed point

adcxIData — Real part of ADC output

scalar | column vector

Real part of ADC output, returned as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of adcxIData ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxIData ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

adcxQData — Imaginary part of ADC output

scalar | column vector

Imaginary part of ADC output, returned as a scalar or column vector with length from 1 to N, where N is the number of samples per clock cycle that you specify in the Samples per clock cycle parameter.

x indicates the number of adcxQdata ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxQdata ports.

For more information about the data format, see Data Format Between RF Data Converter Block and Hardware Logic.

Dependencies

To enable this port, set the Digital interface parameter to I/Q.

Data Types: uint16 | uint32 | uint64 | fixed point

adcxValid — Indication of valid ADC output data

Boolean scalar

Indication of valid ADC output data, returned as a Boolean scalar.

A value of 1 indicates that the data on the adcxData port is valid or that the data on the adcxIData and adcxQData ports is valid.

x indicates the number of adcxValid ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface sets the number of adcxValid ports.

Data Types: Boolean

adcxRealTimeCtrlOut — ADC real-time control output

bus

ADC real-time control output, returned as a bus.

x indicates the number of adcxRealTimeCtrlOut ports and ranges from 1 to m, where m is the maximum number of ADCs available on the selected hardware board. The RF interface parameter sets the number of adcxRealTimeCtrlOut ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has two output ports, one per ADC channel interface.

Note

This port is always set to Low as the RF Data Converter block does not support simulation of the NCO mixer.

Dependencies

To enable this port, select Real-time ports on the Advanced tab.

Data Types: RFDC2DUTRealTimeCtrlBusObj

dacTileyNCOUpdateBusy — Indication that DAC NCO update is in progress

Boolean scalar

Indication that DAC NCO update is in progress, returned as a Boolean scalar.

y indicates the number of dacTileyNCOUpdateBusy ports and ranges from 1 to k, where k is the maximum number of DAC tiles available on the selected hardware board. The RF interface parameter sets the number of dacTileyNCOUpdateBusy ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has one output port, one per DAC tile.

Note

This port is always set to Low as the RF Data Converter block does not support simulation of the NCO mixer.

Dependencies

To enable this port, select Real-time NCO ports under the DAC section on the Advanced tab.

Data Types: Boolean

adcTileyNCOUpdateBusy — Indication that ADC NCO update is in progress

Boolean scalar

Indication that ADC NCO update is in progress, returned as a Boolean scalar.

y indicates the number of adcTileyNCOUpdateBusy ports and ranges from 1 to k, where k is the maximum number of ADC tiles available on the selected hardware board. The RF interface parameter sets the number of adcTileyNCOUpdateBusy ports. For example, if you set the RF interface parameter to ADC & DAC 2x2 RF Interface, the block has one output port, one per ADC tile.

Note

This port is always set to Low as the RF Data Converter block does not support simulation of the NCO mixer.

Dependencies

To enable this port, select Real-time NCO ports under the ADC section on the Advanced tab.

Data Types: Boolean

Parameters

Hardware board — View selected hardware

None (default) | supported Xilinx boards

This parameter is read-only.

For details about how to choose a hardware board and configure its parameters, see Hardware Implementation Pane.

RF interface — RF interface selection

ADC & DAC 2x2 RF Interface (default) | ADC & DAC 1x1 RF Interface | ADC & DAC 4x4 RF Interface | ADC & DAC 8x8 RF Interface | ADC & DAC 16x16 RF Interface | Customize

Specify the RF channel interface type.

To select a predefined set of ADC and DAC combinations, set this parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. Available options for this parameter vary as per the selected hardware board. To select the required number of DAC or ADC combinations, set this parameter to Customize.

Example: ADC & DAC 2x2 RF Interface specifies two ADC and two DAC RF channel interfaces.

Digital interface — Digital interface selection

Real (default) | I/Q

Specify the digital interface type.

• Real – Supports real data

• I/Q – Supports complex data by using real and imaginary ports

DAC

The number of panes and number of DACs in each pane in the DAC tab depend on the selected hardware board. The tiles and DACs shown on the block mask indicate the corresponding tiles and DACs on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the DAC tab contains two panes (Tile1 and Tile2), and each pane contains four DACs. For a ZCU111 board, DAC1, DAC2, DAC3, and DAC4 in Tile1 correspond to DAC 0, DAC 1, DAC 2, and DAC 3 in DAC tile 228, respectively. DAC5, DAC6, DAC7, and DAC8 in Tile2 correspond to DAC 0, DAC 1, DAC 2, and DAC 3 in DAC tile 229, respectively.

The selection of tiles and the respective DACs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. You cannot modify the tile and DAC selection when you select these predefined options. To modify the tile and DAC selections, set the RF interface parameter to Customize.

Match parameters of all DACs — Matching parameters of all DACs

on (default) | off

Select this parameter to apply the same parameter values to all of the selected DACs.

Clear this parameter to specify different parameter values for each of the selected DACs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Sample rate (MSPS) — Data sample rate

1000 (default) | scalar

Specify the sample rate as a scalar in a range that is based on the selected hardware board. Units are in mega samples per second.

For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the sample rate must be in the range [500, 6554].

Interpolation mode (xN) — Interpolation factor

2 (default) | 1 | 3 | 4 | 5 | 6 | 8 | 10 | 12 | 16 | 20 | 24 | 40

Specify the interpolation factor.

Note

Gen 1 and Gen 2 devices support interpolation factors of 1, 2, 4, and 8. Gen 3 devices support interpolation factors of 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, and 40.

Samples per clock cycle — Number of samples per clock cycle

2 (default) | 1 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16

Specify the number of samples per clock cycle. Available options for the number of samples per clock cycle vary with the selected hardware board and digital interface type.

The block calculates the stream data width as 16 x Samples per clock cycle.

The block calculates the stream clock frequency as Sample rate (MSPS) / Interpolation mode (xN) x Samples per clock cycle.

Mixer type — Mixer type

Bypassed (default) | Coarse | Fine

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

Mixer mode — Mixer mode type

Real->Real (default) | I/Q->Real

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use I/Q->Real, set the Digital interface parameter to I/Q.

Mixer frequency — Frequency of mixer

Fs/2 (default) | Fs/4 | -Fs/4

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

NCO frequency (GHz) — NCO frequency

[0 0] (default) | integer in the range [–10, 10]

Specify the NCO frequency values as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

NCO phase — NCO phase

[0 0] (default) | integer in the range [–180, 180]

Specify the NCO phase as an m-element row vector, where m is the number of DACs.

When you set the RF interface parameter to Customize and clear the Match parameters of all DACs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter to Fine.

Inverse sinc filter — Flat-out response

off (default) | on

Select this parameter to convert the analog sinc output response from the DAC to a flat-output response.

ADC

The number of panes and number of ADCs in each pane in the ADC tab depend on the selected hardware board. The tiles and ADCs shown on the block mask indicate the corresponding tiles and ADCs on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the ADC tab contains four panes (Tile1, Tile2, Tile3, and Tile4), and each pane contains two ADCs. For a ZCU111 board, ADC1 and ADC2 in Tile1 correspond to ADC 0 and ADC 1 in ADC tile 224, respectively. ADC3 and ADC4 in Tile2 correspond to ADC 0 and ADC 1 in ADC tile 225, respectively. ADC5 and ADC6 in Tile3 correspond to ADC 0 and ADC 1 in ADC tile 226, respectively. ADC7 and ADC8 in Tile4 correspond to ADC 0 and ADC 1 in ADC tile 227, respectively.

The selection of tiles and the respective ADCs is predefined when you set the RF interface parameter to ADC & DAC 1x1 RF Interface, ADC & DAC 2x2 RF Interface, ADC & DAC 4x4 RF Interface, ADC & DAC 8x8 RF Interface, or ADC & DAC 16x16 RF Interface. You cannot modify the tile and ADC selection when you select these predefined options. To modify the tile and ADC selections, set the RF interface parameter to Customize.

Output data as frame — Option to output data as frame of samples

on (default) | off

Select this parameter to output data as a frame of samples. Clear this parameter to output data as a scalar.

Match parameters of all ADCs — Matching parameters of all ADCs

on (default) | off

Select this parameter to apply the same parameter values to all of the selected ADCs.

Clear this parameter to specify different parameter values for each of the selected ADCs.

Dependencies

To enable this parameter, set the RF interface parameter to Customize.

Sample rate (MSPS) — Data sample rate

1000 (default) | scalar

Specify the sample rate as a scalar in a range that is based on the selected hardware board. Units are in mega samples per second.

For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the sample rate must be in the range [1000, 4096].

Decimation mode (xN) — Decimation factor

2 (default) | 1 | 3 | 4 | 5 | 6 | 8 | 10 | 12 | 16 | 20 | 24 | 40

Specify the decimation factor.

Note

Gen 1 and Gen 2 devices support decimation factors of 1, 2, 4, and 8. Gen 3 devices support decimation factors of 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, and 40.

Samples per clock cycle — Number of samples per clock cycle

2 (default) | 1 | 3 | 4 | 5 | 6 | 7 | 8 | 10 | 11 | 12 | 14 | 16

Specify the number of samples per clock cycle. Available options for the number of samples per clock cycle vary with the selected hardware board and digital interface type.

The block calculates the stream data width as: 16 x Samples per clock cycle.

The block calculates the stream clock frequency as: Sample rate (MSPS) / Decimation mode (xN) x Samples per clock cycle.

Mixer type — Mixer type

Bypassed (default) | Coarse | Fine

Specify the mixer type.

To use Bypassed, set the Digital interface parameter to Real.

To select either Coarse or Fine, set the Digital interface parameter to I/Q.

Mixer mode — Mixer mode type

Real->Real (default) | Real->I/Q

This parameter is read-only.

To use Real->Real, set the Digital interface parameter to Real.

To use Real->I/Q, set the Digital interface parameter to I/Q.

Mixer frequency — Frequency of mixer

Fs/2 (default) | Fs/4 | -Fs/4

Specify the mixer frequency.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Coarse.

NCO frequency (GHz) — NCO frequency

[0 0] (default) | integer in the range [–10, 10]

Specify the numerically controlled oscillator (NCO) frequency values as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

NCO phase — NCO phase

[0 0] (default) | integer in the range [–180, 180]

Specify the NCO phase as an m-element row vector, where m is the number of ADCs.

When you set the RF interface parameter to Customize and clear the Match parameters of all ADCs parameter, m must be 1.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and Mixer type parameter to Fine.

Advanced

Common Parameters

Multi tile sync — Multitile synchronization

off (default) | on

Select this parameter to enable MTS.

In generation, the Xilinx RF Data Converter tool provides synchronization clocks and ADC and DAC clocks to the RF Data Converter hardware IP. In MTS mode, these synchronization clocks depend on the ADC and DAC sampling rates. Because, the Xilinx RF Data Converter tool provides a set of fixed default synchronization clocks in MTS mode and supports only these sample rates: 737.28, 1474.56, 1966.08, 2457.6, 2949.12, 3072, 3932.16, 4669.44, 4915.2, 5898.24, and 6144.

For more information on MTS mode, see Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269) in the Xilinx documentation.

External PLL — Option to enable external PLL

off (default) | on

Select this parameter to enable the external phase-locked loop (PLL).

Each ADC and DAC tile includes an internal PLL. This internal PLL together with a clocking instance provides ADC and DAC clocks for each tile as per the ADC or DAC sampling rates. When you select this parameter, the internal PLL disables, and the clocking circuit directly provides ADC and DAC clocks for each tile. The Xilinx RF Data Converter tool supports only these external PLL clock frequencies: 737.28, 1474.56, 1966.08, 2048, 2457.6, 2949.12, 3072, 3194.88, 3276.8, 3686.4, 3932.16, 4096, 4423.68, 4669.44, 4915.2, 5734.4, 5898.24, 6144, 6389.76, 6400, and 6553.6.

DAC

Real-time NCO ports — Option to add real-time NCO ports for DAC

off (default) | on

Select this parameter to add real-time NCO ports for the DAC. You can use these ports to modify the NCO frequency and phase during run time.

For more information on real-time NCO ports, see Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269) in the Xilinx documentation.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter on the DAC tab to Fine.

ADC

Real-time NCO ports — Option to add real-time NCO ports for ADC

off (default) | on

Select this parameter to add real-time NCO ports for the ADC. You can use these ports to modify the NCO frequency and phase during run time.

For more information on real-time NCO ports, see Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269) in the Xilinx documentation.

Dependencies

To enable this parameter, set the Digital interface parameter to I/Q and the Mixer type parameter on the ADC tab to Fine.

Real-time ports — Option to add real-time ports for ADC

off (default) | on

Select this parameter to add real-time ports for the ADC. Selecting this parameter enables the threshold monitoring circuit, which compares the ADC sampled data with the specified threshold values.

For more information on real-time ports and threshold settings, see Zynq UltraScale+ RFSoC RF Data Converter Gen 1/2/3/DFE LogiCORE IP Product Guide (PG269) in the Xilinx documentation.

Threshold1 mode — Threshold mode for first threshold

Sticky over (default) | Sticky under | Hysteresis

Select threshold mode for the first threshold as one of these options.

• Sticky over — Set the threshold status signal to High when the ADC sampled data exceeds the threshold value that you set in the Threshold1 parameter. The threshold status signal remains High until you set the PLEvent signal in the adcxRealTimeCtrlIn input bus port to High.

• Sticky under — Set the threshold status signal to High when the ADC sampled data remains below the threshold value, which you set in the Threshold1 parameter, for the number of samples that you set in the Number of sample(s) below threshold1 parameter. The threshold status signal remains High until you set the PLEvent signal in the adcxRealTimeCtrlIn input bus port to High.

• Hysteresis — Set the threshold status signal to High when the ADC sampled data exceeds the upper threshold value. Set the threshold status signal to Low when the ADC sampled data remains below the lower threshold value for the number of samples that you specify in the Number of sample(s) below threshold1 parameter.

Dependencies

To enable this parameter, select Real-time ports.

Threshold1 — Threshold value for first threshold

0 (default) | scalar | column vector

Specify the threshold value for the first threshold. For the sticky over threshold mode, this value serves as the upper threshold value. For the sticky under threshold mode, this value serves as the lower threshold value. For the hysteresis threshold mode, specify the threshold values in the format [T_lower T_upper], where T_lower is the lower threshold value and T_upper is the upper threshold value.

Dependencies

To enable this parameter, select Real-time ports.

Number of sample(s) below threshold1 — Number of samples below threshold value for first threshold

0 (default) | positive integer

Specify the number of samples below the threshold value for the first threshold.

Dependencies

To enable this parameter, set the Threshold1 mode parameter to Sticky under or Hysteresis.

Threshold2 mode — Threshold mode for second threshold

Sticky over (default) | Sticky under | Hysteresis

Select threshold mode for the second threshold as one of these options.

• Sticky over — Set the threshold status signal to High when the ADC sampled data exceeds the threshold value that you set in the Threshold2 parameter. The threshold status signal remains High until you set the PLEvent signal in the adcxRealTimeCtrlIn input bus port to High.

• Sticky under — Set the threshold status signal to High when the ADC sampled data remains below the threshold value, which you set in the Threshold2 parameter, for the number of samples that you set in the Number of sample(s) below threshold2 parameter. The threshold status signal remains High until you set the PLEvent signal in the adcxRealTimeCtrlIn input bus port to High.

• Hysteresis — Set the threshold status signal to High when the ADC sampled data exceeds the upper threshold value. Set the threshold status signal to Low when the ADC sampled data remains below the lower threshold value for the number of samples that you specify in the Number of sample(s) below threshold2 parameter.

Dependencies

To enable this parameter, select Real-time ports.

Threshold2 — Threshold value for second threshold

0 (default) | scalar | column vector

Specify the threshold value for the second threshold. For the sticky over threshold mode, this value serves as the upper threshold value. For the sticky under threshold mode, this value serves as the lower threshold value. For the hysteresis threshold mode, specify the threshold values in the format [T_lower T_upper], where T_lower is the lower threshold value and T_upper is the upper threshold value.

Dependencies

To enable this parameter, select Real-time ports.

Number of sample(s) below threshold2 — Number of samples below threshold value for second threshold

0 (default) | positive integer

Specify the number of samples below the threshold value for the second threshold.

Dependencies

To enable this parameter, set the Threshold2 mode parameter to Sticky under or Hysteresis.

More About

Data Format Between RF Data Converter Block and Hardware Logic

In general, the interface from the hardware logic to the ADC and DAC operates at a single sample per clock cycle. However, the RF Data Converter block can operate on single or multiple samples per clock cycle, where each sample is of 16 bits. You must select the number of samples per clock cycle based on your input data.

For example, to send four samples per clock cycle, first concatenate these samples. Then, provide the concatenation as a 64-bit input to the block and set the Samples per clock cycle parameter to 4. The block outputs 64-bit data, which comprises four 16-bit samples.

These figures show the input format to the DAC and the output format from the ADC when the RF interface parameter is set to ADC & DAC 1x1 RF Interface and the Digital interface parameter is set to Real.

These figures show the input format to the DAC and the output format from the ADC when the RF interface parameter is set to ADC & DAC 1x1 RF Interface and the Digital interface parameter is set to I/Q.

Extended Capabilities

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2020a

R2020b: Change in output valid port of RF Data Converter block

In R2020a, the RF Data Converter block has two valid ports adcxIValid and adcxQValid corresponding to I and Q data ports adcxIData and adcxQdata, respectively.

In R2020b, the two valid output ports adcxIValid and adcxQValid are removed and replaced with one output port adcxValid that corresponds to both I and Q data ports. When you open a model containing an RF Data Converter block that was created in R2020a and has its Digital interface parameter set to I/Q, the output ports of the block might not be correctly connected.

In this case, manually check and correct the port connections in your model to proceed further.