Main Content

Zynq and FMCOMMS2/3/4 Receiver Configuration

Connect hardware logic to FMCOMMS Zynq radio receiver hardware

Since R2019a

expand all in page
  • Zynq and FMCOMMS2/3/4 Receiver Configuration block

Libraries:
SoC Blockset Support Package for Xilinx Devices / SDR / AD9361

Description

The Zynq and FMCOMMS2/3/4 Receiver Configuration block connects to the FMCOMMS2/3/4 radio receiver hardware in your hardware logic. In simulation, this block provides optional ports for center frequency and gain, which the SoC Builder tool maps to hardware pins. The block does not connect to the radio hardware from simulation.

Examples

Packet-Based ADS-B Transceiver

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Ports

Input

expand all

External RF center frequency, specified as a nonnegative finite scalar on the port. The valid center frequency range is from 70 MHz to 6 GHz.

Dependencies

To enable this port, set the Source of center frequency parameter to Input port.

Data Types: double

External gain, specified as a numeric scalar. The valid gain range is –10 dB to 77 dB. The resolution is 0.25 dB.

Dependencies

To enable this port, set the Source of gain parameter to Input port.

Data Types: double

Parameters

expand all

Source of center frequency, specified as one of these options:

  • Dialog — Set the center frequency by using the Center frequency (Hz) parameter.

  • Input port — Set the center frequency by using the center frequency input port.

RF center frequency, in Hz, specified as a nonnegative scalar. The valid range for center frequency is 70 MHz to 6 GHz.

Dependencies

To enable this parameter, set the Source of center frequency to Dialog.

Data Types: double

Source of gain, specified as one of these options:

  • Dialog — Specify the gain by using the Gain (dB) parameter.

  • Input port — Specify the gain by using the gain input port.

  • AGC Slow Attack –– Use this mode for signals with a slowly changing power level.

  • AGC Fast Attack –– Use this mode for signals with a rapidly changing power level.

Gain, in dB, specified as a numeric scalar. The valid gain range is -10 dB to 77 dB. The resolution is 0.25 dB.

Dependencies

To enable this parameter, set Source of gain to Dialog.

Data Types: double

Baseband sampling rate, in Hz, specified as a positive scalar. The valid range of this parameter is 520.834 kHz to 61.44 MHz.

Data Types: double

Advanced

When you select this parameter, the block applies in-phase and quadrature (IQ) imbalance compensation.

When you select this parameter, the block applies an RF direct current (DC) blocking filter.

When you select this parameter, the block applies a baseband DC blocking filter.

Extended Capabilities

Version History

Introduced in R2019a

See Also