C28x-Clocking

Use the clocking options to achieve the CPU clock rate specified on the board. The default clocking values run the CPU clock (CLKIN) at its maximum frequency. The parameters use the external oscillator frequency on the board (OSCCLK) that is recommended by the processor vendor.

For F2837xD and F2838xD dual-core processor, the clock settings are available only when you select the CPU1 option in the Build options > Select CPU parameter. When you select CPU2 option in the Build options > Select CPU parameter, set the CPU clock with the value available in the Achievable SYSCLKOUT in MHz parameter for the CPU1 model.

You can get feedback on the closest achievable SYSCLKOUT value with the specified oscillator clock frequency by selecting the Auto set PLL based on OSCCLK and CPU clock check box. Alternatively, you can manually specify the PLL value for the SYSCLKOUT value calculation.

Change the clocking values if:

You want to change the CPU frequency.
The external oscillator frequency differs from the value recommended by the manufacturer.

To determine the CPU frequency (CLKIN), use the following equation:

CLKIN = (OSCCLK × PLLCR) / (DIVSEL or CLKINDIV)

Where,

CLKIN is the frequency at which the CPU operates, also known as the CPU clock.
OSCCLK is the frequency of the oscillator.
PLLCR is the PLL control register value.
CLKINDIV is the clock in the divider.
DIVSEL is the divider select.

The availability of the DIVSEL or CLKINDIV parameters changes depending on the processor that you select. If neither parameter is available, use the following equation:

CLKIN = (OSCCLK × PLLCR) / 2

You can set the following parameters for clocking:

Desired C28x CPU clock in MHz

Specify the desired CPU clock frequency (CLKIN). This value is taken automatically for Achievable SYSCLKOUT in MHz = (OSCCLK×PLLCR)/DIVSEL.

CPU Clock in MHz (C28SYSCLK/SYSCLKOUT)

Enter the value that you specified for Desired C28x CPU clock in MHz. This parameter is available only for TI Concerto F28M35x/ F28M36x processors. For more information, see the PLL-Based Clock Module section in the Texas Instruments^® Reference Guide for your processor.

Use internal oscillator

Use the internal zero pin oscillator on the CPU. This parameter is enabled by default.

Oscillator clock (OSCCLK) frequency in MHz

Oscillator frequency used in the processor. This parameter is not available for TI Concerto F28M35x/ F28M36x processors.

Note

By default the clock source value is set to 20MHz.

Early versions of the controlCARDs (MCU063E1, MCU063E2, MCU063A) use a 20 MHz clock while newer versions of TI F2838x control cards starting from MCU063B and later use a 25 MHz input clock.

Auto set PLL based on OSCCLK and CPU clock

PLL values in PLLCR, DIVSEL, and Achievable SYSCLKOUT in MHz are automatically calculated based on the CPU clock entered on the board. This parameter is not available for TI Concerto F28M35x/ F28M36x processors.

PLL control register (PLLCR)

If you select Auto set PLL based on OSCCLK and CPU clock, the auto calculated control register value achieves the specified CPU clock value, based on the oscillator clock frequency. Alternatively, you can select a value for PLL control register (PLLCR). This parameter is supported only on specific C28x devices. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.

System PLL multiplier (SYSPLLMULT) [1-127]

PLL output divider (ODIV)/System PLL output divider (SYSPLLMULT_ODIV)

Calculates SYSCLKOUT = ((OSCCLK×SYSPLLMULT)/ODIV)/SYSDIVSEL. This parameter is supported only on specific C28x devices.

Clock divider (DIVSEL)/System clock divider (SYSDIVSEL)

If you select Auto set PLL based on OSCCLK and CPU clock, the auto calculated control register value achieves the specified CPU clock value, based on the oscillator clock frequency. Alternatively, you can select a value for Clock divider (DIVSEL). This parameter is supported only on specific C28x devices. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.

System PLL raw clock value in MHz: PLLRAWCLK = ((OSCCLK*SYSPLLMULT_IMULT)/SYSPLLMULT_ODIV)

System PLL raw clock value is calculated based on oscillator clock and SYSPLLMULT_IMULT. This parameter is supported only on specific C28x devices. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.

PLL reference divider (SYSPLLMULT_REFDIV)

If you select Auto set PLL based on OSCCLK and CPU clock, the auto calculated control register value achieves the specified CPU clock value, based on the oscillator clock frequency. Alternatively, you can select a value for PLL reference divider (SYSPLLMULT_REFDIV). This parameter is supported only on specific C28x devices.

Achievable SYSCLKOUT in MHz: PLLSYSCLK = ((OSCCLK/SYSPLLMULT_REFDIV)*SYSPLLMULT_IMULT)/SYSPLLMULT_ODIV)/SYSDIVSEL

The auto calculated feedback value that matches the Desired C28x CPU clock in MHz value, based on the values of PLLSYSCLK, PLLCR, and DIVSEL. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.

Set the 'Achievable SYSCLKOUT in MHz = (OSCCLK*SYSPLLMULT)/SYSDIVSEL' value calculated in CPU1

Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Achievable SYSCLKOUT in MHz = (OSCCLK*PLLCR)/DIVSEL (auto calculated).

Select the 'Low-Speed Peripheral Clock Prescaler (LSPCLK)' option used in CPU1: Available only for CPU2 of dual C28x core processors. Value of this parameter must be same as the value of the parameter Low-Speed Peripheral Clock Prescaler (LSPCLK) specified in CPU1.
Low-Speed Peripheral Clock Prescaler (LSPCLK): The value using which LSPCLK is scaled. This value is based on SYSCLKOUT.
Low-Speed Peripheral Clock (LSPCLK) in MHz: The value is calculated based on LSPCLK Prescaler. Example: SPI uses a LSPCLK.
High-Speed Peripheral Clock Prescaler (HSPCLK): The value using which HSPCLK is scaled. This value is based on SYSCLKOUT.
High-Speed Peripheral Clock (HSPCLK) in MHZ: The value is calculated based on HSPCLK Prescaler. Example: ADC uses a HSPCLK.
Multiplication factor for PLL#CLK (PLL#MULT): The multiplication factor value of PLL clock.
PLL clock in MHz (PLLCLK) = OSCCLK*PLLCR: The value is calculated based on Multiplication factor for PLL#CLK (PLL#MULT) and OSCCLK frequency.
Analog Subsystem Clock Prescaler (ASYSCLK): The value using which ASYSCLK is scaled. This value is based on SYSCLKOUT. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.
Analog Subsystem Clock (ASYSCLK): The value calculated using the SYSCLKOUT and ASYSCLK Prescaler values. This parameter is not supported on TI Concerto F28M35x or F28M36x processors.
Connectivity Manager (Arm Cortex-M4) clock source: Select the clock source for Arm Cortex-M4 core. This source provides input to the CM clock divider. Select System PLL or Auxiliary PLL as the clock source. This parameter is supported only on specific C28x devices.
Desired Connectivity Manager (Arm Cortex-M4) clock in MHz: Specify the desired CPU clock frequency (CMCLKIN). This value is taken automatically for Achievable Connectivity Manager (Arm Cortex-M4) clock in MHz: CMCLK = (AUXPLLRAWCLK or PLLRAWCLK) / (CMCLKDIV). This parameter is supported only on specific C28x devices and when parameter Connectivity Manager (Arm Cortex-M4) clock source is set to Auxiliary PLL.
Connectivity Manager (Arm Cortex-M4) clock divider (CMCLKDIV): Select the divider for the Arm Cortex-M4 core clock. The divider adjusts the signal from the clock source to generate the Arm Cortex-M4 core clock. This parameter is supported only on specific C28x devices.
Auxiliary PLL clock source: Select the auxiliary PLL clock source. By default, auxiliary PLL clock source is set to Internal oscillator. You can configure it to use the Internal oscillator, External oscillator (XTAL), or Auxiliary clock (GPIO 133). This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auxiliary oscillator clock (AUXOSCCLK) frequency in MHz: Specify the auxiliary PLL output divider. By default, the auxiliary PLL output divider is set to 10. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auto set Auxiliary PLL based on AUXOSCCLK and desired CM clock: Enable auxiliary PLL values on AUXOSCCLK and desired CM clock are automatically calculated based on the CM clock entered on the board. PLL values in AUXPLLMULT_ODIV, AUXPLLMULT_IMULTDIVSEL, and AUXPLLMULT_REFDIV are automatically calculated based on the desired CM clock and AUXOSCCLK frequency entered on the board. This parameter is not available for TI Concerto F28M35x/ F28M36x processors. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auxiliary PLL output divider (AUXPLLMULT_ODIV): Specify the auxiliary PLL output divider. By default, the auxiliary PLL output divider is set to 10. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auxiliary PLL multiplier (AUXPLLMULT_IMULT): Specify the auxiliary PLL multiplier. By default, the auxiliary PLL multiplier is set to 40. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auxiliary PLL reference divider (AUXPLLMULT_REFDIV): Specify the auxiliary PLL reference divider. By default, the auxiliary PLL reference divider is set to 1. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Auxiliary PLL raw clock value in MHz: AUXPLLRAWCLK = (((AUXOSCCLK/AUXPLLMULT_REFDIV)*AUXPLLMULT_IMULT)/AUXPLLMULT_ODIV): By default, the auxiliary PLL raw clock value in MHz is set to 400. Auxiliary PLL raw clock value is calculated based on AUXOSCCLK, AUXPLLMULT_REFDIV, AUXPLLMULT_IMULT, and AUXPLLMULT_ODIV. This parameter is supported only on specific C28x devices and requires the parameter Connectivity Manager (Arm Cortex-M4) clock source to be set to Auxiliary PLL.
Achievable Connectivity Manager (Arm Cortex-M4) clock in MHz: CMCLK = (AUXPLLRAWCLK or PLLRAWCLK) / (CMCLKDIV): The calculated value of the clock frequency (in MHz) supplied to Arm Cortex-M4 core. This parameter is supported only on specific C28x devices.

C28x-Clocking

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