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C28x-DMA_ch#

The Direct Memory Access (DMA) module transfers data directly between peripherals and memory using a dedicated bus, increasing overall system performance. In this case, # represents the DMA channel number.

You can individually enable and configure each DMA channel.

The DMA module services are event driven. Using the Interrupt source parameter, you can configure a wide range of peripheral interrupt event triggers. For more information, see the technical reference manual of your processor.

You can set the following parameters for DMA:

Enable DMA channel

Enable this parameter to edit the configuration of a specific DMA channel. This parameter does not have a corresponding bit or register.

Data size

Select the size of the data bit transfer.

The DMA read/write data buses are 32 bits wide. 32-bit transfers have twice the data throughput of a 16-bit transfer.

When providing DMA service to McBSP, set Data size to 16 bit.

The following parameters are based on a 16-bit word size. If you set Data size to 32 bit, double the value of the following parameters:

  • Size: Burst

  • Source: Burst step

  • Source: Transfer step

  • Source: Wrap step

  • Destination: Burst step

  • Destination: Transfer step

  • Destination: Wrap step

Data size corresponds to bit 14 (DATASIZE) in the mode register (MODE).

Interrupt source

Select the peripheral interrupt that triggers a DMA burst for the specified channel.

Different C2000™ processors have different interrupt trigger options that can be configured to trigger the DMA. Depending on the processor, the trigger sources include peripheral interrupts from ePWM, ADC, SPI, timer, and external interrupt. Some of these interrupt triggers such as TINT0 may require manual configuration. For external interrupt using GPIO, the configuration is done in the External Interrupt tab.

The Interrupt source parameter corresponds to bit 4–0 (PERINTSEL) in the mode register (MODE).

Burst size

Specify the number of 16-bit words in a burst, from 1 to 32. The DMA module must complete a burst before it can service the next channel.

Set the burst size for the peripheral DMA module services. For the ADC, the value equals the number of ADC registers used, up to 16. For multichannel buffered serial ports (McBSP), which lack FIFOs, the value is 1.

For RAM, the value can range from 1–32.

This parameter corresponds to bits 4–0 (BURSTSIZE) in the burst size register (BURST_SIZE).

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Transfer size

Specify the number of bursts in a transfer, from 1–65536.

This parameter corresponds to bits 15–0 (TRANSFERSIZE) in the transfer size register (TRANSFER_SIZE).

Source begin address

Set the starting address for the current source address pointer. The DMA module points to this address at the beginning of a transfer and returns to it as specified by the SRC wrap parameter.

This parameter corresponds to bits 21–0 (BEGADDR) in the active source begin register (SRC_BEG_ADDR).

Destination begin address

Set the starting address for the current destination address pointer. The DMA module points to this address at the beginning of a transfer and returns to it as specified by the DST wrap parameter.

This parameter corresponds to bits 21–0 (BEGADDR) in the active destination begin register (DST_BEG_ADDR).

Source burst step

Set the number of 16-bit words using which the current address pointer is incremented or decremented before the next burst. Enter a value from –4096 (decrement) to 4095 (increment).

To disable incrementing or decrementing the address pointer, set Burst step to 0. For example, because McBSP does not use FIFO, configure DMA to maintain the sequence of the McBSP data by moving each word of the data individually.

Accordingly, when you use DMA to transmit or receive McBSP data, set Burst size to 1 word and Burst step to 0.

This parameter corresponds to bits 15-0 (SRCBURSTSTEP) in the source burst step size register (SRC_BURST_STEP).

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Destination burst step

Set the number of 16-bit words using which the current address pointer is incremented or decremented before the next burst. Enter a value from –4096 (decrement) to 4095 (increment).

To disable incrementing or decrementing the address pointer, set Burst step to 0. For example, because McBSP does not use FIFO, configure DMA to maintain the sequence of the McBSP data by moving each word of the data individually. Accordingly, when you use DMA to transmit or receive McBSP data, set Burst size to 1 word and Burst step to 0.

This parameter corresponds to bits 15–0 (DSTBURSTSTEP) in the destination burst step size register (DST_BURST_STEP).

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Source transfer step

Set the number of 16-bit words using which the current address pointer is incremented or decremented before the next transfer. Enter a value from –4096 (decrement) to 4095 (increment).

To disable incrementing or decrementing the address pointer, set Transfer step to 0.

This parameter corresponds to bits 15–0 (SRCTRANSFERSTEP) source transfer step size register (SRC_TRANSFER_STEP).

If DMA is configured to perform memory wrapping (SRC wrap enabled), the corresponding source Transfer step does not alter the results.

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Destination transfer step

Set the number of 16-bit words using which the current address pointer is incremented or decremented before the next transfer. Enter a value from –4096 (decrement) to 4095 (increment).

To disable incrementing or decrementing the address pointer, set Transfer step to 0.

This parameter corresponds to bits 15–0 (DSTTRANSFERSTEP) destination transfer step size register (DST_TRANSFER_STEP).

If DMA is configured to perform memory wrapping (DST wrap enabled), the corresponding destination Transfer step does not alter the results.

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Source wrap size

Specify the number of bursts before returning the current source address pointer to the Source Begin Address value. To disable wrapping, enter a value that is greater than the Transfer value.

This parameter corresponds to bits 15-0 (SRC_WRAP_SIZE) in the source wrap size register (SRC_WRAP_SIZE).

Destination wrap size

Specify the number of bursts before returning the current destination address pointer to the Destination Begin Address value. To disable wrapping, enter a value that is greater than the Transfer value.

This parameter corresponds to bits 15-0 (DST_WRAP_SIZE) in the destination wrap size register (DST_WRAP_SIZE).

Source wrap step

Set the number of 16-bit words using which the SRC_BEG_ADDR address pointer is incremented or decremented when a wrap event occurs. Enter a value from –4096 (decrement) to 4095 (increment).

This parameter corresponds to bits 15–0 (WRAPSTEP) in the source wrap step size registers (SRC_WRAP_STEP).

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Destination wrap step

Set the number of 16-bit words using which the DST_BEG_ADDR address pointer is incremented or decremented when a wrap event occurs. Enter a value from –4096 (decrement) to 4095 (increment).

This parameter corresponds to bits 15–0 (WRAPSTEP) in the destination wrap step size registers (DST_WRAP_STEP).

Note

This parameter is based on 16-bit word size. If you set Data size to 32 bit, double the value of this parameter.

Set channel 1 to highest priority

This parameter is available only for DMA_ch1.

Enable this option when DMA channel 1 is configured to handle high-bandwidth data, such as ADC data, and the other DMA channels are configured to handle lower-priority data. When enabled, the DMA module services each enabled channel sequentially until it receives a trigger from channel 1. Upon receiving the trigger, DMA interrupts its service to the current channel at the end of the current word, services the channel 1 burst that generated the trigger, and then continues servicing the current channel at the beginning of the next word.

Disable this channel to give each DMA channel equal priority, or if DMA channel 1 is the only enabled channel. When disabled, the DMA module services each enabled channel sequentially.

This parameter corresponds to bit 0 (CH1PRIORITY) in the priority control register 1 (PRIORITYCTRL1).

Enable first DMA event to trigger the full transfer (one shot mode)

Enable this parameter to have the DMA channel complete an entire transfer in response to an interrupt event trigger.

This option allows a single DMA channel and peripheral to dominate resources, and may streamline processing, but it also creates the potential for resource conflicts and delays.

Disable this parameter to have DMA complete one burst per channel per interrupt.

This parameter appears only when Set channel 1 to highest priority is disabled.

Synchronize ADC interrupt event triggers to DMA wrap counter (sync mode)

Enable this parameter to reset the DMA wrap counter when the Interrupt source is set to SEQ1INT and sends the ADCSYNC signal to the DMA wrap counter. This way, the wrap counter and the ADC channels remain synchronized with each other.

If Interrupt source is not set to SEQ1INT, Sync enable does not alter the results.

This parameter corresponds to bit 12 (SYNCE) of the mode register (MODE).

Do not disable the DMA channel after the transfer is complete (continuous mode)

Select this parameter to leave the DMA channel enabled upon completing a transfer. The channel waits for the next interrupt event trigger.

Clear this parameter to disable the DMA channel upon completing a transfer. The DMA module disables the DMA channel by clearing the RUNSTS bit in the control register when it completes the transfer. To use the channel again, first reset the RUN bit in the control register.

Enable destination sync mode

Enabling this parameter resets the destination wrap counter (DST_WRAP_COUNT) when Sync enable is enabled and the DMA module receives the SEQ1INT interrupt/ADCSYNC signal.

Disabling this parameter resets the source wrap counter (SCR_WRAP_COUNT) when the DMA module receives the SEQ1INT interrupt/ADCSYNC signal.

This parameter is associated with bit 13 (SYNCSEL) in the mode register (MODE).

This parameter appears only when Synchronize ADC interrupt event triggers to DMA wrap counter (sync mode) is selected.

Generate interrupt

Enable this parameter to have the DMA channel send an interrupt to the CPU via the PIE at the beginning or end of a data transfer.

This parameter corresponds to bit 15 (CHINTE) and bit 9 (CHINTMODE) in the mode register (MODE).

Enable overflow interrupt

Enable this parameter to have the DMA channel send an interrupt to the CPU via PIE if the DMA module receives a peripheral interrupt while a previous interrupt from the same peripheral is waiting to be serviced.

This parameter is used for debugging during the development phase of a project.

The Enable overflow interrupt parameter corresponds to bit 7 (OVRINTE) of the mode register (MODE), and involves the overflow flag bit (OVRFLG) and peripheral interrupt trigger flag bit (PERINTFLG).

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