sample time mismatch
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after implementing a signal builder instead of single Steps, I get the following message:
"Incoming buses to block 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch' have a sample time mismatch. The signal at input port 1 of 'Thermoschock_aktuell/Rohr/Bus Creator' is of sample time [0, 0], while its corresponding signal at input port 1 of 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Bus Creator' is of sample time [0, 1]. This error message is related to a hidden SubSystem block."
This will happen with some multiport-switches in 'Thermoschock_aktuell/3-Wege-Ventil 1e2a/Switch'. I've currently no idea, why it works with steps, but not with signal builders.
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Arnaud Miege
il 12 Lug 2011
One of your busses has a continuous sample time, while the other one a discrete sample time of 1s. Use a rate transition block to convert the continuous one to a discrete one with a sample time of of 1s.
HTH,
Arnaud
Guy Rouleau
il 13 Lug 2011
In the Signal builder, go to the file menu, there is an option to set the sample time. Change it from 0 to 1.
I recommend enabling sample time colors to better understand this sort of issues. This is done form the Format menu of the model.
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