How can I make a connection between FPGA and Simulink?
I want to use FPGA-In-the-Loop (FIL) and my purpose is performing altera board Stratix iv and Simulink.
I try to do this steps (https://www.mathworks.com/help/hdlverifier/ug/block-generation-with-the-fil-wizard.html) for my project and this example. I have a similar error in both cases ( failed to receive a control packet from fpga target ) .
Please leave any suggestions.