The idea is to generate the HDL IP blocks using the external PL DDR3 memories with both AXI4 Master and AXIS interfaces. The data are sent in in AXIS mode, lots of memory intensive calculation is done using the AXI4 Master read/write IF and then the data are read out in the AXIS mode, as shown in Fig. 1.
In the workadvisor flow, the protocol mapping for the external memory DDR3 interface is limited to AXI4 Master read and write, and there is no other mapping left for the protocol mapping for streaming data in. Shown in Fig. 2.
What is the best way to have multiple AXI interfaces for the IP block generation?