I am new to Simulink but with long experience in FPGA design using VHDL, and I am trying to implement a filter using fixed point data format by reusing a single filter tap in Simulink. The reason to do this is that I must use the total structure in two different ways : a) use the full tap length b) use one third of the tap length (decimated taps, and coeficcients). No predefined Simulink FIR block can be used for that. The second major constraint is that the filter structure + control of it must be able to generate VHDL.
Essentially , I want to reuse a filter tap description to get the VHDL code for a symmetric FIR by reusing the Simulink diagram for a single tap and writing some logic around this diagram to choose which taps do I use. In VHDL I would do this writing manually the code for a tap, and re-instantiating it by using a FOR GENERATE loop, which the adequate wiring of inputs , outputs, but I have no idea on what type of Simulink structure allows for that replication.