Using MATLAB and FPGA-in-the-Loop to design a filter.

Versione 1.0 (2,84 MB) da Pablo Trujillo Juan
Workflow to design, test, verify and implement a filter on FPGA.
5.0
(1)
172 download
Aggiornato 20 dic 2020
Visualizza la licenza su GitHub

This project describes the entire workflow to design a filter and implement it on an FPGA.
- Study the filter requirements.
- Design the filter using Filter Designer tool.
- Test the filter, and the quantified filter on MATLAB and Simulink.
- Generate the HDL code of the filter.
- Verify the filter on the corresponding device using FPGA-in-the-Loop
- Integrate the filter on a Vivado design and test it on the application.

Cita come

Pablo Trujillo Juan (2024). Using MATLAB and FPGA-in-the-Loop to design a filter. (https://github.com/controlpaths/line_filtering/releases/tag/1.0), GitHub. Recuperato .

Compatibilità della release di MATLAB
Creato con R2020b
Compatibile con qualsiasi release
Compatibilità della piattaforma
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Versione Pubblicato Note della release
1.0

Per visualizzare o segnalare problemi su questo componente aggiuntivo di GitHub, visita GitHub Repository.
Per visualizzare o segnalare problemi su questo componente aggiuntivo di GitHub, visita GitHub Repository.