Answered

'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

8 mesi ago | 0

| accepted

Answered

How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

8 mesi ago | 0

| accepted

Answered

Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

9 mesi ago | 0

Answered

I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

9 mesi ago | 0

Answered

HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

10 mesi ago | 0

Answered

Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

10 mesi ago | 1

Answered

How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

11 mesi ago | 0

Answered

Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

11 mesi ago | 0

Answered

How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

12 mesi ago | 0

Answered

Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

12 mesi ago | 0

Answered

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

12 mesi ago | 0

| accepted

Answered

How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

circa un anno ago | 0

| accepted

Answered

MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

circa un anno ago | 0

Answered

Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

circa un anno ago | 0

Answered

how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

circa un anno ago | 0

Answered

How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

circa un anno ago | 1

Answered

How can i watch the content of a HDL RAM Block during simulation

I do not believe this capability exists currently. Could you please get in touch with MATLAB support to register this request so...

How can i watch the content of a HDL RAM Block during simulation

I do not believe this capability exists currently. Could you please get in touch with MATLAB support to register this request so...

circa un anno ago | 0

Answered

The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!

There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can mode...

The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!

There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can mode...

circa un anno ago | 0

| accepted

Answered

QPSK Modulation Verilog Code generation error?

It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...

QPSK Modulation Verilog Code generation error?

It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...

circa un anno ago | 0

| accepted

Answered

I'm getting this error and I'm unable to figure out this. Please help

Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...

I'm getting this error and I'm unable to figure out this. Please help

Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...

circa un anno ago | 0

Answered

HDL Coder streaming input instead of vector

In this case, you want to use the Unbuffer block to stream the data in sample by sample.

HDL Coder streaming input instead of vector

In this case, you want to use the Unbuffer block to stream the data in sample by sample.

oltre un anno ago | 0

| accepted

Answered

How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...

How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...

oltre un anno ago | 0

Answered

How to configure modelsim in Matlab?

You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...

How to configure modelsim in Matlab?

You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...

circa 2 anni ago | 1

Answered

Matlab HDL coder target frequency

The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...

Matlab HDL coder target frequency

The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...

circa 2 anni ago | 0

Answered

Discrete FIR Filter input port

As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...

Discrete FIR Filter input port

As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...

circa 2 anni ago | 0

Answered

'vsim' requires HDL Verifier.

If you are trying to co-simulate MATLAB code and HDL code in ModelSim, you will need the HDL Verifier product to do so.

'vsim' requires HDL Verifier.

If you are trying to co-simulate MATLAB code and HDL code in ModelSim, you will need the HDL Verifier product to do so.

oltre 2 anni ago | 1

Answered

LTE HDL MIB Recovery block explanation

The LTE Toolbox example on Cell Search has further information and MATLAB code that you can run. For the HDL implementation, yo...

LTE HDL MIB Recovery block explanation

The LTE Toolbox example on Cell Search has further information and MATLAB code that you can run. For the HDL implementation, yo...

oltre 2 anni ago | 0

| accepted

Answered

How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

As shown in the example, the HDL FFT needs into the separated out into a separte design file. The example puts the HDL-optimized...

How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

As shown in the example, the HDL FFT needs into the separated out into a separte design file. The example puts the HDL-optimized...

oltre 2 anni ago | 0

Answered

Implementing scanning indow using HDL FIFOs

We have a block that does the windowing - please look at the Line Buffer block. I believe this will meet your needs.

Implementing scanning indow using HDL FIFOs

We have a block that does the windowing - please look at the Line Buffer block. I believe this will meet your needs.

oltre 2 anni ago | 0

Answered

F-OFDM filtering for 5G

You are right - this is not a formal part of the 5G standard. You can look at this example to see how F-OFDM behaves vs. OFDM. ...

F-OFDM filtering for 5G

You are right - this is not a formal part of the 5G standard. You can look at this example to see how F-OFDM behaves vs. OFDM. ...

oltre 2 anni ago | 0

| accepted