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Differences in Performance Between Simulink and Matlab FIRs
Could you please pass along a complete script that runs? I think Fs=30e6 from your comments, but I do not have data defined.

quasi 7 anni fa | 0

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Differences in Performance Between Simulink and Matlab FIRs
I suggest using the the Discrete FIR Filter block with the coefficients you used for MATLAB. If that works, it is the easiest wa...

quasi 7 anni fa | 0

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How to use boolean to control switch with fixed point data.
S1 and S2 when they are assigned to mealy_state_reg likely need to be fixed point. Try using assignements as follows: mealy_st...

quasi 7 anni fa | 0

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RTL generation error: Signal rate of value inf found
If you turn on sample time colors in your model, you should be able to see where the inf sample time is being set.

quasi 7 anni fa | 0

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can someone please help about NCO HDL optimized block. How to generate a simple sine wave with it. I am gettting a single straight line as output for what ever phase increment i use. can someone help how to set sampling frequency as well
Attached is a simple NCO which generates a sine wave. Phase increment is set to 4 and accumulator size is 8 bits, so you will se...

quasi 7 anni fa | 0

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How to use a vector of complex data as source in HDL coder?
Attached is a simple model that shows how to stream in a 4 value complex vector one value at a time. The values are split into r...

quasi 7 anni fa | 0

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HDL code to simulink model
You can use an HDL Cosimulation block to import this into Simulink. Here is a video and documentation for the procedure.

quasi 7 anni fa | 0

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How to generate HDL serial filter architecture form Digital Down-Converter example
It does not apply to the CIC, please try it for the FIR Filter.

quasi 7 anni fa | 0

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How can I figure out how many delay units do I need in one part of Simulink HDL design?
One of the ways to do this is by logging the input and output signals to the Logic Analyzer. You can set your cursors on the inp...

quasi 7 anni fa | 0

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How to generate HDL serial filter architecture form Digital Down-Converter example
You can take each of the filters through the process of HDL code generation to control how many resources to use. To do so, run ...

quasi 7 anni fa | 0

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Problem Using/Doing FFT HDL Optimized
Please take a look at this example which shows how to use the HDL Optimized FFT block.

quasi 7 anni fa | 0

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HDL Coder disable Clock Enable output port
There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on th...

quasi 7 anni fa | 0

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HDL Coder disable Clock Enable output port
You can use the option Minimize Clock Enables to remove the clock enable port. The clock enable typically cannot be removed for ...

quasi 7 anni fa | 0

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Is it possible to get a conceptual explanation of how the scanning window filter work using the HDL pixel stream interface
The Line Buffer block help page has a brief description of its algorithm. The page also also has an example on how to construct ...

quasi 7 anni fa | 0

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HDL COSIMULATION is taking too long time
You can use he FIL Frame To Pixels and FIL Pixels To Frame blocks - these send in multiple pixels at at time a line or frame at ...

quasi 7 anni fa | 0

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FFT on FPGA using HDL coder
You can use the HDL Optimized FFT block for HDL code generation. Can you clarify on what challenges you face for fixed point co...

quasi 7 anni fa | 0

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How can I create a subsystem which performs the opposite of the Multiport Switch block?
What output do you expect for each of these output signals in HDL? Say you have 10 outputs, your input is 1, and you want to se...

circa 7 anni fa | 0

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Estimating the latency of a custom IP block in HDL Coder
One of the ways to do this is by having the computatiobn block emit a valid output signal. based on this signal, the controller ...

circa 7 anni fa | 0

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HDL Coder VHDL Output
fix14 implies that there are 14 bits in total. u implies unsigned. En15 indicates that the LSB has a value of 2^-15, with an in...

circa 7 anni fa | 0

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How to profile an HDL Subsystem?
If you synthesize your HDL design in the appropriate HDL tool (example: Vivado), you will know what clock speed you can run the ...

circa 7 anni fa | 0

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how to generate sine wave for fpga?
You can use the self-guided tutorial on HDL Coder to see how to use the tool. The HDL Optimized NCO block in Simulink will allow...

circa 7 anni fa | 0

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FPGA-in-the-Loop (FIL) Simulink Block Creation
Does your HDL code handle single datatype pixel input? You may want to try it with the appropriate fixed-point pixel data that t...

circa 7 anni fa | 0

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How to plot n bit series of numbers. (n = 16 for example)
You can have a similar display using the dsp.LogicAnalyzer object. Here is the sample code I used: data = fi(rand(100,1),1,16,1...

circa 7 anni fa | 0

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Is there any hdl library available for pulse generator. If yes please tell me the link
You can use the NCO HDL Optimized block to generate sine or cosine waves. Other repetitve waveforms can be genrated using a RAM...

circa 7 anni fa | 0

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conv2 'valid' implementation
You can use the MATLAB workflow in the example for image filtering.

circa 7 anni fa | 0

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conv2 'valid' implementation
If you are looking for conv2 for image filtering, you can use the ImageFilter <https://www.mathworks.com/help/visionhdl/ref/imag...

oltre 7 anni fa | 0

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Size mismatch using reshape in HDL Coder
Could you try assigning the value to a different variable rather than back to A. Ar = reshape(A,8,8); use Ar in the code bel...

oltre 7 anni fa | 0

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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can shar...

oltre 7 anni fa | 0

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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?
The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbenc...

oltre 7 anni fa | 0

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Matlab Simulink hardware design - Do we need a third party simulator?
You can run the generated HDL and testbench in the vivido simulator. However, if you want to run HDL cosimulation (that is, runn...

oltre 7 anni fa | 0