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Tom Richter

MathWorks

Last seen: 10 giorni fa |  Attivo dal 2023

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  • 6 Month Streak
  • Knowledgeable Level 2
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Risposto
Digital Down Converter: # Samples must be Integer multiple of decimation factor
Hi Egor, I agree with Fangjun and suggest contacting Technical Support to help you with this issue/question. If you go to htt...

22 giorni fa | 0

Risposto
How to set Unconditional Transition State for Else Statement in HDL Coder with a Counter?
Hello Michael, This is a good catch. Have you tried to use the “after” temporal logic operator on a smaller design? Did the Syn...

22 giorni fa | 0

| accettato

Risposto
Is it possible to do an Inference on an Artix7 esp. a Digilent Nexys Video Board?
Hi Silas, I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com...

circa un mese fa | 1

Risposto
Good FPGA for learning MATLAB for signal processing and comm
Hello Bogdan, You find information about supported hardware here. There are boards from AMD (Xilinx), Altera (Intel), and Mic...

circa un mese fa | 1

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Risposto
Field-Oriented Control on FPGA SoC and Vivado Design Suite - HLx Editions - 2020.1
Hi Aleksander, in the current version of MATLAB R2023b we support Vivado 2022.1 for this Trenz Motor Control example. If you wa...

circa un mese fa | 0

Risposto
Can you use switches as inputs in a design tested with FPGA-in-the-Loop simulation? (on a Zedboard)
Hi Julien, FIL is just for testing an algorithm independently of any peripherals. What you like to do is FPGA Prototyping. S...

circa un mese fa | 0

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Risposto
How to configure Kria KV260 Vision AI Starter Kit for FPGA-in-the-loop with Simulink?
Hi Fabio, I suggest contacting Technical Support to help you with this issue/question. If you go to https://www.mathworks.com/s...

2 mesi fa | 0

Risposto
Deep Learning Network on a Xilinx Cora Z7-10
Hi Martin, You can use Deep Learning HDL Toolbox to deploy a network on FPGAs/SoSs from AMD or Intel. We don't support your boa...

3 mesi fa | 1

Risposto
Why do I receive the error "Unable to perform assignment because the left and right sides have a different number of elements." in step 3.2 of HDL Workflow Advisor?
Hi Gorka, Have you tried to run the HDL WA with a new project name (Step 1.1)? If this does not help, please share more informa...

3 mesi fa | 0

Risposto
Simulink/HDLVerifier : error setting property 'status' of class 'CosimWizardPkg.CosimWizardDlg'. Value must contain ASCII characters
Hi Christophe, In the current MATLAB release (R2023b) we only support: Questa® Core/Prime 2022.4 ModelSim® PE 2022.4 ...

4 mesi fa | 0

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Risposto
Using a persistent variable array in MATLAB function for HDL Coder
Hi Kaan, it would be good if you could share your MATLAB code you try to implement using the MATLAB Function block. For me it s...

5 mesi fa | 0

Risposto
Generic data type configuration based on reference precision.
Here the file I used (R2023b).

5 mesi fa | 0

Risposto
Generic data type configuration based on reference precision.
Hi Eirik, Okay, I think I understand now what you need. First, you only have 27 bits data not 29. Therefore, you want to map th...

5 mesi fa | 0

Risposto
adi rf som gpio options
Hi Raz, Let me use a shipping example "HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364". I change...

5 mesi fa | 0

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Risposto
FPGA Data Capture speed
Hello Jiri, This is quite an ambitious goal. The example "Stream Audio Signal from Intel FPGA Board Using Ready-to-Capture Sign...

5 mesi fa | 0

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Using Custom I/Q Sample on "GPS HDL Acquisition and Tracking Using C/A Code" Example
Hi Kaan, it depends on the range of your I/Q samples. In the example the data type is converted from double to fixed-point. Her...

5 mesi fa | 0

Risposto
FIL I/O options missing in the FIL wizard.
Hi Charanraj, I assume you refer to the FIL I/O panel in the FPGA Board Wizard of the FPGA Board Manager. You can access the FP...

5 mesi fa | 0

Risposto
How do i define an array as a HDL input?
Starting in R2022a, HDL Coder supports matrix types inputs and outputs at the DUT interface. This enhancement reduces the overhe...

6 mesi fa | 2

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Risposto
Implementing Variable Delay Length in Simulink Model for HDL Code Generation
Starting in R2022a, you can generate HDL code for the Variable Integer Delay block. You can now generate code for Delay block th...

6 mesi fa | 0