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Alexander Kiermayer


Hochschule Rosenheim

3 total contributions since 2016

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Using Unit Delays in triggered Subsystems for HDL Codegeneration
I solved the problem. I had a Limited Counter for triggering the subsystem. After replacing it by an HDL counter, everything i...

circa 2 anni ago | 0

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Using Unit Delays in triggered Subsystems for HDL Codegeneration
Hi, i'm having some Unit Delays in a Triggered Subsystem. When generating VHDL Code using Mathworks HDL Coder I get the foll...

circa 2 anni ago | 2 answers | 0

2

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Question


HDL Coder generates VHD Files for Sample and Hold Blocks
Hi, I'm using Sample and Hold Blocks in my design. When I generate the VHDL Code, I get files named like "controlss_block.vhd"...

oltre 2 anni ago | 0 answers | 0

0

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