Risposto
AD9467 HDL Coder adding Custom Reference Design - create_bc_cell issue
The Vivado error message is complaining that it cannot find an IP (analog.com:user:axi_ad9467:1.0) when HDL Workflow Advisor is ...

oltre 10 anni fa | 0

Risposto
How to use the Unit Delay for HDL-Coder on Zedboard Zynq-7000?
Hi Jan, when you run the model on Zynq board, the FPGA part of the design is running at a fast frequency (50MHz). When you are u...

oltre 10 anni fa | 1

| accettato

Risposto
[Coretcl 2-106] Specified part could not be found
Hi Diego, it looks like the Vivado tool you have do not have xc7z045 device support. Are you using Xilinx Vivado Webpack edition...

oltre 10 anni fa | 0

Risposto
HDL Coder - Generate IP Core with Vivado 2015
Hi Zachary, which MATLAB version are you using? If you are using MATLAB and HDL Coder R2015b, the supported Vivado version is Vi...

oltre 10 anni fa | 0

Risposto
HDL WORKFLOW ADVISOR (Errors)
Hi RAJASHEKAR, as the error message sugguested: "Target platform "Xilinx Spartan-6 SP605 development board" requires synthesis...

oltre 10 anni fa | 1

Risposto
Worflow advisor tcl scripts generates error at programming phase
Hi Antti, This is a limitation of current HDL Workflow Advisor (R2015b). There is no option to configure the JTAG programming...

quasi 11 anni fa | 0

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Risposto
what is the difference between FPGA Turnkey and IP Core Generation?
Hi Yashar, Both IP Core Generation and FPGA Turnkey workflows can help you prototype your Simulink/MATLAB algorithm on FPGA/S...

quasi 11 anni fa | 10

| accettato

Risposto
Generate C code for FPGA
Hi Ran, The recommended workflow is to use HDL Coder to generate HDL Code and IP core for Altera SoC FPGA fabric, and use Emb...

circa 11 anni fa | 1

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Risposto
HDL Coder Workflow Advisor timing analysis
Hi Grégory, You can open Xilinx ISE project from the link generated in HDL Workflow Advisor step 4.1, and change following tw...

oltre 11 anni fa | 0

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Risposto
Is HDL Coder capable of generating configurable code?
Hi Ethan, GENERIC/PARAM is supported by HDL Coder when you use "Generate parameterized HDL code from masked subsystem" featur...

quasi 12 anni fa | 0

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Risposto
Using HDL Coder IP core in Xilinx Vivado instead of EDK
Hi Stefan, Yes, the IP core generation feature for Xilinx Vivado will be supported in MATLAB R2014b release. You can already...

circa 12 anni fa | 0

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Risposto
unable to load valid reference design plugin
Hi Roger, In HDL Workflow Advisor Step 1.2 "Set Target Interface", In the table "Target platform interface table", do you have o...

oltre 12 anni fa | 0

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Risposto
ZedBoard full Linux for MathWorks HDL Coder
Hi Amir, Ubuntu or any other Linux flavor is not supported by HDL Coder and Embedded Coder support package for Zynq/ZedBoard in...

oltre 12 anni fa | 0

| accettato

Risposto
how could i generate an axi-stream or axi4-lite dma master by hdl coder?
Hi Owen, HDL Coder doesn't support AXI4-Lite Master mode yet. The current AXI4-Lite support is for slave mode only. You can u...

oltre 12 anni fa | 1

Risposto
HDL Stream FFT in HDL Coder 2013b, not support FPGA?
Hi Owen, The HDL Streaming FFT block only support signed fixed-point data type as input. You can try change your input data t...

quasi 13 anni fa | 0

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Risposto
HDL Stream FFT in HDL Coder 2013b, not support AXI4-Stream Interface? (single rate?)
Hi Owen, The HDL Streaming FFT block is not yet supported by AXI4-Stream Video interface in 2013b (because this block uses mu...

quasi 13 anni fa | 0

Risposto
is it possible to work with Altera Cyclone(EP1C12Q240C8) FPGA kit and Matlab HDL workflow advisor ?
Hi Kingsuk, Both the FPGA-in-the-loop and FPGA Turnkey workflow does not support Altera Cyclone FPGA family. The supported FP...

quasi 14 anni fa | 0

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Risposto
Altera FPGAs
Hi Natalie, Yes, you need a separate Altera FPGA board to prototype Altera Arria II Gx FPGA. Altera FPGA boards are suppor...

circa 14 anni fa | 0

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