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Error " Dot indexing is not supported for variable of this type" comes when tried to configure HDL Coder support package for Xilinx Zynq Platform.
MathWorks team is investigating the issue and will provide an update shortly. Any additional reproduction steps are helpful (mac...

oltre 4 anni fa | 0

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Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
Here is an example of HDL Coder friendly current control algorithm for your reference. Field-Oriented Control of a Permanent Ma...

oltre 4 anni fa | 0

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Assertion failed: B:\matlab\src\cgir_hdl\pir_backend\SubsystemLowering.cpp:1189:triggerRate != -1
This example is not compatible with HDL Code Generation. Reaching to the development team for suggestions on HDL Coder compatibl...

oltre 4 anni fa | 1

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matlab hdl coder error
See detailed examples of how to perform HDL Code Generation from MATLAB — Examples

quasi 5 anni fa | 0

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How to build a model that is efficient for HDL conversion?
DVB-S2 HDL PL Header Recovery This example shows how to implement DVB-S2 time, frequency, and phase synchronization and PL head...

quasi 5 anni fa | 1

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Simulink model not editable
This example shows how to implement a QPSK transmitter and receiver in Simulink® that is optimized for HDL code generation and h...

quasi 5 anni fa | 0

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HDL Coversion of Simulink code
HDL QPSK Transmitter and Receiver This example shows how to implement a QPSK transmitter and receiver in Simulink® that is opti...

quasi 5 anni fa | 0

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how to convert matlab code in VHDL ? which tool boxes to download?
You need to partition the MATLAB code into design and testbench files and create a HDL Coder project. Try a sample MATLAB to HD...

quasi 5 anni fa | 0

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How i can import an existing IP Core in Vivado in Simulink as block?
These links show how to integrate custom RTL code into a model targeted for HDL code generation using HDL Coder https://www.mat...

quasi 5 anni fa | 0

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HDL coder fails generating wavelet denoise function
Support for C/C++ code generation exists for wdenoise. I have reported the HDL Code Generation request for this function to dev...

quasi 5 anni fa | 0

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Using std_logic_vector(0 downto 0) in HDL Coder
Unfortunately this coding style switch is not currently available. I have communicated this request with the development team. ...

quasi 5 anni fa | 0

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error in dlhdl.buildProcessor(hPCNew) step
Can you share the version of MATLAB you are using?

quasi 5 anni fa | 1

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Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
We are unable to reproduce the issue on our end with the attached models. Please reach out to support for additional help on thi...

quasi 5 anni fa | 0

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how to create bit from image to feed as input to xilinx multiplier block in system generator
Check this example on how to convert a frame to a sample and feed the sample into FPGA >> mlhdlc_demo_setup('heq')

quasi 5 anni fa | 0

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Unable to create project in xilinx vivado 2015.2 from simulink using hdl workflow adviser,Getting error [12-172],how can get pass this?
https://www.mathworks.com/help/hdlcoder/ug/using-ip-core-generation-from-matlab.html Generate Custom HDL IP Core for Blinking L...

quasi 5 anni fa | 0

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hdl coder IO buffer error
Answering the question without access to the model or the full context here. You could consider enabling the resource utiliza...

quasi 5 anni fa | 1

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HDL Coder removes I/Os of a model reference when they are terminated inside the model reference
Remove Redundant Logic and Unused Blocks in Generated HDL Code https://www.mathworks.com/help/hdlcoder/ug/remove-redundant-lo...

quasi 5 anni fa | 0

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Generate HDL Code for Simscape Models
The model does not show failures in HDL Coder R2020a and R2020b releases. Can you please sure additional information or reach o...

quasi 5 anni fa | 0

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Inferring RAM zero index issue
Can you MATLAB code (dut.m) and a Testbench (dut_tb.m) and the project file with MATLAB to HDL codegen settings? This example...

quasi 5 anni fa | 0

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Explanation of "Assertion failed port already connected to signal error" when generating using HDL Coder?
This is an unexpected internal error. Reported to the development team. Can you let us know what version of MATLAB / HDL Coder...

quasi 5 anni fa | 0

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Generate HDL Code for Simscape Models
Can you share your Simscape model?

quasi 5 anni fa | 0

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Generating HDL from a Random Number Generator
The mask on the uniform generator has sample time and seed parameters. The uniform generator produces uint32 ...

quasi 5 anni fa | 1

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Domanda

Generating HDL from a Random Number Generator
How do I model Random Number Generator suitable for HDL Coder?

quasi 5 anni fa | 1 risposta | 0

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Multiple outputs from HDL block in simulink
https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-interface-in-zynq-workflow.html Getting Started wit...

quasi 5 anni fa | 0

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Activation Network Connection Failed in Hardware Setup
Contact support@mathworks.com with reproduction steps.

quasi 5 anni fa | 0

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Multiple outputs from HDL block in simulink
Can you share your model? Thanks

quasi 5 anni fa | 0

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How do you make D-FF for HDL coders in simulink?
Hardware Modeling with MATLAB Code MATLAB® design and test bench guidelines for HDL code generation Model for HDL Code Gener...

quasi 5 anni fa | 0

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HDL code for 'findpeak' function
please find attached a pulse detector example. You can find a similar thread here.

quasi 5 anni fa | 0

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POW2(A) is not supported when A is a FI object.
You are using Variable dimensions and the coding style is not suitable for HDL Code generation or FPGA/ASIC synthesis. Few...

quasi 5 anni fa | 0

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POW2(A) is not supported when A is a FI object.
Please share your design.m and testbench.m and MATLAB to HDL project file. Thanks

quasi 5 anni fa | 0