The Avnet Spartan-3A DSP DaVinci Development Kit provides an engineering platform for evaluating and integrating the Xilinx Spartan 3A-DSP FPGA and TI digital media processor based on DaVinci™ technology. The platform includes the XC3SD1800ADSP FPGA and the TMS320DM6437 digital media processor with both high-speed data and low-speed control interfaces between the two devices. The board also provides several peripheral and interface functions and an EXP expansion slot for custom add-on modules. The platform is well suited to applications where an FPGA and DSP coexist, such as compute-intensive products in industrial imaging, video security, automotive, and machine vision.
The development kit also includes full-featured evaluation software from Xilinx, Texas Instruments, and MathWorks, enabling customers to quickly explore various development methodologies. Avnet and MathWorks provide additional driver support for the Avnet coprocessing platform, enabling users to adopt Model-Based Design for developing their DSP and FPGA applications.
Using Model-Based Design, developers can graphically model and simulate their system with MATLAB® and Simulink® and leverage add-on toolboxes and blocksets from MathWorks for video and image processing. Once the system design is verified through simulation, MathWorks tools support design partitioning and implementation onto both the DSP and FPGA. For the DSP, Simulink Coder® creates C code and drivers for the DSP implementation based on the Simulink models. This feeds into Code Composer Studio™ from TI for compilation and DSP programming. For the FPGA, Simulink works with System Generator for DSP from Xilinx. System Generator provides Xilinx-specific blocks to Simulink for the creation of HDL output. This output feeds into the ISE Foundation software.
Avnet provides a board support package (BSP) with drivers for the DSP peripherals such as the video processing front end (VPFE), video processing back end (VPBE), and VLYNQ interfaces. The Avnet BSP also provides HDL code examples for the various hardware interfaces to the FPGA. These code examples offer proven building blocks for the larger FPGA system. MathWorks also provides a board support package with blocksets that allow Simulink to target the interfaces between the DSP and the FPGA. This enables users to evaluate system partitioning scenarios between the two without having to manage much of the low-level design details. Once implemented, DSP and FPGA debug and validation can take place through hardware and software cosimulation capabilities included in the Simulink workflow.
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