Static Analysis Target Specification for Common Processors

This topic lists the target configurations for Polyspace^® static analysis of C/C++ code tailored for common processor families. If you are manually setting up a Polyspace project for static analysis, use the specifications below to indicate the processor family.

vPIC32 (Microchip PIC32 MIPS)

Microchip's PIC32 family of processors is based on the MIPS32 architecture, used in high-performance 32-bit embedded applications.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target true,8,2,4,-1,4,8,4,4,8,4,8,1,little,unsigned_long,long,int
-D __XC
-D __XC32
-D __PIC32

PIC16 (Microchip PIC24/dsPIC)

PIC24 and dsPIC processors are 16-bit MCU and DSP-enabled MCU families widely used in embedded control applications.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target true,8,2,2,-1,4,8,4,4,8,2,2,1,little,unsigned_int,int,long
-D __XC16

XC8 (Microchip PIC10/12/16/18)

These 8-bit PIC microcontrollers are commonly used in low-power, cost-sensitive embedded applications.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target false,8,2,2,-1,4,8,4,4,4,2,1,1,little,unsigned_int,int,long
-D __XC8

Xtensa

Xtensa is a configurable processor architecture widely used in SoCs, including ESP32-class microcontrollers.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target false,8,2,4,-1,4,8,4,8,8,4,8,1,little,unsigned_int,int,short
-D __XTENSA__

TriCore

Infineon’s TriCore architecture combines MCU, DSP, and RISC features, commonly used in automotive and safety-critical systems.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target true,8,2,4,-1,4,8,4,8,8,4,4,1,little,unsigned_int,int,int
-D __tc

ARM

ARM processors are widely used 32-bit RISC architectures found in embedded systems, mobile devices, and microcontrollers.

If you are manually configuring static analysis for this family of processors, set these options:

-target arm
-D __arm__

ARM64

ARM64 (AArch64) is the 64-bit evolution of ARM, supporting higher performance and larger memory addressing.

If you are manually configuring static analysis for this family of processors, set these options:

-target arm64
-D __aarch64__

RISC-V

RISC-V is an open, modular 32-bit instruction set architecture increasingly used in embedded and academic environments.

If you are manually configuring static analysis for this family of processors, set these options:

-target riscv
-D __riscv
-D __riscv_xlen=32

RISC-V64

The 64-bit version of the RISC-V instruction set, used in higher-performance embedded and Linux-capable platforms.

If you are manually configuring static analysis for this family of processors, set these options:

-target riscv64
-D __riscv
-D __riscv_xlen=64

PowerPC

PowerPC is a 32-bit RISC architecture historically used in industrial, automotive, and legacy embedded systems.

If you are manually configuring static analysis for this family of processors, set these options:

-target powerpc
-D __powerpc__

PowerPC64

PowerPC64 extends the architecture to 64 bits, supporting larger memory and more advanced embedded workloads.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target false,8,2,4,-1,8,8,4,8,16,8,16,1,little,unsigned_long,long,int
-D __powerpc__
-D __powerpc64__

MSP430

Texas Instruments’ MSP430 family is a low-power 16-bit microcontroller line optimized for ultra-low-energy applications.

If you are manually configuring static analysis for this family of processors, set these options:

-custom-target false,8,2,2,-1,4,8,4,8,8,2,2,1,little,unsigned_int,int,int
-D __MSP430__

See Also

Processor (-custom-target) | -target