HDL Code Generation and Deployment

Generate HDL code using HDL Coder™, verify code using HDL Verifier™, and prototype designs using hardware support packages

DSP HDL Toolbox™ provides blocks and System objects that support HDL code generation. To generate HDL code from these designs, you must have HDL Coder. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

If you have an HDL Verifier license, you can use the FPGA-in-the-loop feature to prototype your HDL design on an FPGA board. HDL Verifier also enables you to cosimulate a Simulink^® model with an HDL design running in a third-party simulator.

To design, prototype, and verify domain-specific practical applications on hardware, download hardware support packages such as SoC Blockset™ Support Package for AMD FPGA and SoC Devices and HDL Coder Support Package for Xilinx^® FPGA and SoC Devices.

Topics

Prototype DSP HDL Algorithms on Hardware
Prototype DSP HDL Toolbox designs on FPGA and SoC boards using hardware support packages.
Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder)
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Host Interface Script Data Capture from Polyphase Channelizer Algorithm (HDL Coder)
Capture ADC data to external DDR memory and display the resulting spectrum plot using FPGA API functions over a TCP/IP connection.
Multi-Tile Synchronization Configuration (HDL Coder)
Use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device.

Related Information

HDL Coder
HDL Verifier

Featured Examples

Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design

Design and simulate data path using SoC Blockset on Xilinx RFSoC device.

(SoC Blockset)

Transmit and Receive Tone Using AMD RFSoC Device - Part 2 Deployment

Implement and verify design using SoC Blockset on Xilinx RFSoC device.

(SoC Blockset)