dsphdl.FarrowRateConverter

Polynomial sample-rate converter

Since R2022a

Description

The dsphdl.FarrowRateConverter System object™ converts the sample rate of a signal by using FIR filters to implement a polynomial sinc approximation. A Farrow filter is an efficient rate converter when the rate conversion factor is a ratio of large integer decimation and interpolation factors. Specify the rate conversion factor by providing the input sample rate and the desired output sample rate. You can provide the rate conversion factor as a fixed property or as a time-varying input signal.

You can use this object with the default coefficients for most rate conversions. The default coefficients are a LaGrange interpolation that matches the dsp.FarrowRateConverter System object. Or, you can specify a custom set of coefficients if the default does not meet your specifications.

The object provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the object models architectural latency including pipeline registers and multiplier optimizations.

To filter and resample input data with an HDL-optimized Farrow rate converter:

1. Create the dsphdl.FarrowRateConverter object and set its properties.

2. Call the object with arguments, as if it were a function.

To learn more about how System objects work, see What Are System Objects?

Note

You can also generate HDL code for this hardware-optimized algorithm, without creating a MATLAB^® script, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the System object.

Creation

Syntax

rc = dsphdl.FarrowRateConverter

rc = dsphdl.FarrowRateConverter(Name=Value)

Description

rc = dsphdl.FarrowRateConverter creates an HDL-optimized Farrow filter System object with default properties.

rc = dsphdl.FarrowRateConverter(Name=Value) sets properties using one or more name-value arguments.

For example:

rc = dsphdl.FarrowRateConverter(RateChange=441e3/96e3, ...
                                FilterStructure='Direct form transposed');
[dataOut,validOut,ready] = rc(dataIn,validIn);

Properties

Unless otherwise indicated, properties are nontunable, which means you cannot change their values after calling the object. Objects lock when you call them, and the release function unlocks them.

If a property is tunable, you can change its value at any time.

For more information on changing property values, see System Design in MATLAB Using System Objects.

Main

RateChangeSource — Source of rate change

'Property' (default) | 'Input port'

You can enter a constant rate change as a property or provide a time-varying rate change by using an input argument.

Setting this property to 'Input port' enables the rate argument of the object.

RateChange — Rate change factor

147/160 (default) | positive real scalar

Specify the rate change factor as a ratio of the input sample rate and the output sample rate, Fin/Fout, or provide a rational value. There are no limits on the rate change factor. Specify the data type for this value by using the RateChangeDataType property.

Dependencies

To enable this property, set RateChangeSource to 'Property'.

Data Types: double

Coefficients — FIR filter coefficients

[-1/6 1/2 -1/3 0;1/2 -1 -1/2 1;-1/2 1/2 1 0;1/6 0 -1/6 0] (default) | matrix of real values

Specify FIR filter coefficients as an M-by-N matrix of real values, where N is the number of filters and M is the number of coefficients in each filter. N must be less than six. The object implements a polynomial of order N – 1. The default value is a special closed-form LaGrange solution that accomplishes most rate changes.

Data Types: double

FilterStructure — HDL filter architecture

'Direct form systolic' (default) | 'Direct form transposed'

Specify the HDL filter architecture as one of these structures:

• 'Direct form systolic' — This architecture provides a fully parallel filter implementation that makes efficient use of Intel^® and Xilinx^® DSP blocks. For architecture details, see Fully Parallel Systolic Architecture.

• 'Direct form transposed' — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For architecture details, see Fully Parallel Transposed Architecture.

This object implements the FIR filter stages by using the same architectures as the dsphdl.FIRFilter object. All implementations share multipliers for symmetric and antisymmetric coefficients and remove multipliers for zero-valued coefficients.

NumCycles — Serialization requirement for input timing

1 (default) | positive integer

Serialization requirement for input timing, specified as a positive integer. This property represents N, the minimum number of cycles between valid input samples. To implement a fully serial architecture, set NumCycles to a value greater than the filter length, L, or to Inf.

When this property is greater than one, the object implements each FIR subfilter as a partly-serial architecture that shares the multipliers in time.

Dependencies

To enable this property, set FilterStructure to 'Direct form systolic'.

Data Types

Rounding — Rounding method for type-casting the output

'Floor' (default) | 'Ceiling' | 'Convergent' | 'Nearest' | 'Round' | 'Zero'

Rounding method for type-casting the output, specified as 'Floor', 'Ceiling', 'Convergent', 'Nearest', 'Round', or 'Zero'. The rounding method is used when casting the output to the data type specified by the OutputDataType property. When the input data type is a floating-point data type, the object ignores the RoundingMethod property. For more details, see Rounding Modes.

OverflowAction — Overflow handling for type-casting the output

'Wrap' (default) | 'Saturate'

Overflow handling for type-casting the output, specified as 'Wrap' or 'Saturate'. Overflow handling is used when casting the output to the data type specified by the OutputDataType property. When the input data type is a floating-point data type, the object ignores the OverflowAction property. For more details, see Overflow Handling.

CoefficientsDataType — Data type of discrete FIR filter coefficients

'Same word length as input' (default) | numerictype object

Data type of discrete FIR filter coefficients, specified as 'Same word length as input' or a numerictype object. To specify a numerictype object, call numerictype(s,w,f), where:

• s is 1 for signed and 0 for unsigned.

• w is the word length in bits.

• f is the number of fractional bits.

The object type-casts the filter coefficients of the discrete FIR filter to the specified data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is a floating-point data type, the object ignores this property.

The recommended data type for this parameter is 'Same word length as input'. When selecting this data type, consider the size supported by the DSP blocks on your target FPGA.

RateChangeDataType — Data type of rate change factor

fixdt(1,16) (default) | <data type expression>

The object casts the RateChange property value to this data type and uses this data type to derive the data type for the internal accumulator. The accumulator data type is fixdt(1,fractionalWL+1,fractionalWL), where fractionalWL is the fraction length of the rate change data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is floating point, the object ignores this parameter.

The data type of the rate change must have at least one integer bit and one fractional bit. This data type must have enough integer bits to represent the fsIn/fsOut value. If the data type specified does not have enough integer bits, the object returns an error. The default setting does not specify a number of fractional bits, so the object can compute the necessary integer size. The fractional part of this data type determines the accuracy of the phase timing, but also increases the critical path. When the rate change word length is large, you can limit hardware resources by fitting the multiplicand data type to the DSP blocks on the FPGA.

Dependencies

To enable this port, set the RateChangeSource parameter to 'Property'.

MultiplicandDataType — Data type of multiplicand

'Full precision' (default) | <data type expression>

The object casts the output of the accumulator to this data type. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is a floating-point data type, the object ignores this parameter. When the rate change is large, you can limit hardware resource use by controlling the multiplicand data type. When selecting this data type, consider the size supported by the DSP blocks on your target FPGA.

OutputDataType — Data type of filter output

'Same word length as input' (default) | <data type expression>

The object casts the output of each filter stage to this data type. The quantization uses the settings of the RoundingMethod and OverflowAction properties. When the input data type is a floating-point data type, the object ignores this parameter.

Control Arguments

ResetInputPort — Option to enable reset input argument

false (default) | true

Option to enable the reset input argument, specified as true or false. When you set this property to true, the object expects a value for the reset input argument. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

HDLGlobalReset — Option to connect data path registers to generated HDL global reset signal

false (default) | true

Option to connect the data path registers to the generated HDL global reset signal, specified as true or false. Set this property to true to connect the generated HDL global reset signal to the data path registers. This property does not change the arguments of the object or modify simulation behavior in MATLAB. When you set this property to false, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on your HDL code generation settings.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Usage

Syntax

[dataOut,validOut,ready] = rc(dataIn,validIn)

[dataOut,validOut,ready] = rc(dataIn,validIn, rate)

Description

[dataOut,validOut,ready] = rc(dataIn,validIn) filters the input data only when validIn is true, and returns ready set to true when the object is ready to accept new input data on the next call.

[dataOut,validOut,ready] = rc(dataIn,validIn, rate) filters data to achieve the input to output sample rate ratio, rate. The object expects the rate argument only when you set the RateChangeSource property to 'Input port'. For example:

rc = dsphdl.FarrowRateConverter(RateChangeSource='Input port')
...
for k=1:length(dataIn)
    rate = myGetRate();  %calculate desired rate change
    [dataOut(k),validOut(k)] = rc(dataIn(k),validIn(k),rate);

Input Arguments

dataIn — Input data

real or complex scalar

Input data, specified as a real or complex scalar. When the input data type is an integer type or fixed-point type, the object uses fixed-point arithmetic for internal calculations.

The software supports double and single data types for simulation, but not for HDL code generation.

Data Types: fi | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

validIn — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When validIn is 1 (true), the object captures the values from the dataIn argument. When validIn is 0 (false), the object ignores the values from the dataIn argument.

Data Types: logical

rate — Rate change factor

scalar

Specify the rate change factor as a rational value that is the ratio of the input sample rate and the output sample rate, Fin/Fout. There are no limits on the rate change factor.

When this input value changes, the object resets the internal phase accumulator. This reset means you can change the rate change factor from decimation to interpolation. For example, you can use this object to align data streams that have similar but varying sample clocks.

The data type of the rate change must have at least one integer bit and one fractional bit. The object derives the data type of the internal accumulator from the data type of this signal. The accumulator data type is fixdt(1,fractionalWL+1,fractionalWL), where fractionalWL is the fraction length of the rate change data type. The fractionalWL determines the accuracy of the phase timing, but also increases the critical path. When the rate change word length is large, you can limit hardware resource use by fitting the multiplicand data type to the DSP blocks on the FPGA.

Dependencies

To enable this port, set the RateChangeSource parameter to 'Input port'.

Data Types: fi

reset — Clears internal states

logical scalar

Control signal that clears internal states. When reset is 1 (true), the object stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this argument, set the ResetInputPort property to true.

Data Types: logical

Output Arguments

dataOut — Filtered output data

real or complex scalar

Filtered output data, returned as a real or complex scalar. When the input data type is a floating-point data type, the output data inherits the data type of the input data. When the input data type is an integer type or fixed-point type, the OutputDataType property determines the output data type.

Data Types: fi | single | double
Complex Number Support: Yes

validOut — Indicates valid output data

scalar

Control signal that indicates if the output data is valid. When validOut is 1 (true), the object returns valid data from the dataOut argument. When validOut is 0 (false), values from the dataOut argument are not valid.

Data Types: logical

ready — Indicates object is ready for new input data

logical scalar

Control signal that indicates that the object is ready for new input data sample on the next cycle. When ready is 1 (true), you can specify the data and valid inputs for the next time step. When ready is 0 (false), the object ignores any input data in the next time step.

Data Types: logical

Object Functions

To use an object function, specify the System object as the first input argument. For example, to release system resources of a System object named obj, use this syntax:

release(obj)

Common to All System Objects

step	Run System object algorithm
release	Release resources and allow changes to System object property values and input characteristics
reset	Reset internal states of System object

Algorithms

This System object implements the algorithms described on the Farrow Rate Converter block reference page.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using MATLAB® Coder™.

This System object supports C/C++ code generation for accelerating MATLAB simulations, and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

The software supports double and single data types for simulation, but not for HDL code generation.

To generate HDL code from predefined System objects, see HDL Code Generation from Viterbi Decoder System Object (HDL Coder).

Version History

Introduced in R2022a

R2022b: Partly serial filter architecture

The object now has the NumCycles property to enable resource sharing with a partly serial systolic architecture. The internal FIR filter for each filter stage is implemented with a partly serial systolic filter with the sharing factor that you specify.