Balance delays for generated DUT output ports
Insert matching delays on generated DUT output port paths
Since R2022b
Model Configuration Pane: Global Settings / Ports
Description
Enable this setting to insert matching delays on generated DUT output port paths. Disable this setting to prevent HDL Coder™ from inserting matching delays on paths to output ports generated for test points. Preventing matching delays on test point output port paths in the DUT reduces the amount of resources needed for your design and reduces the latency of test points. Disable this property to probe hardware directly without added latency to the test point signal.
Note
Disabling this property affects the simulation behavior of test points in the original model.
Dependencies
To disable this parameter, select the Enable HDL DUT output port generation for test points check box.
Settings
on
(default) | off
Default: On
on
HDL Coder inserts matching delays on the path of DUT output ports generated for test point signals in the generated HDL code.
off
HDL Coder does not insert matching delays on the path of DUT output ports generated for test point signals in the generated HDL code.
Tips
To set this property, use the functions hdlset_param
or makehdl
. To view the property value, use
the function hdlget_param
.
For example, after you designate signals as testpoints for the sfir_fixed/symmetric_fir
DUT subsystem, to prevent matching delays on the generated DUT output port path in the HDL code, use either of these methods:
Pass the property as an argument to the
makehdl
function.makehdl('sfir_fixed/symmetric_sfir',... 'BalanceDelaysForTestpoints','off')
When you use
hdlset_param
, you can set the parameter on the model, and then generate HDL code by usingmakehdl
.hdlset_param('sfir_fixed','BalanceDelaysForTestpoints','off') makehdl('sfir_fixed/symmetric_fir')
Recommended Settings
No recommended settings.
Programmatic Use
Parameter: BalanceDelaysForTestpoints |
Type: character vector |
Value: 'on' | 'off' |
Default: 'on' |
Version History
Introduced in R2022b