HDL Code Generation
R2026bGenerate HDL code from MATLAB algorithms or Simulink models by using HDL
Coder
Generate Verilog®, SystemVerilog, and VHDL® code for Application-Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) designs. Implement your Simulink® models or MATLAB® algorithms in hardware by generating HDL code and deploying that code on ASICs and FPGAs. If you want to synthesize the generated code on a target device, use the HDL Workflow Advisor. The Advisor can run end-to-end workflows that check HDL compatibility and deploy the generated code to a target device. You can also apply coding styles and make the code conform to industry coding standards.
Categories
- Code Generation from MATLAB Algorithms
Generate HDL code from MATLAB algorithms
- Code Generation from Simulink Models
Generate HDL code from Simulink models
- HDL Workflow Advisor
Deploy the generated code to a target device by using the HDL Workflow Advisor
- Coding Standards
Learn about coding standard report, lint tool scripts, and coding standard rules
- Reports
Generate traceability, optimization, and resource reports
- Synthesis and Timing Analysis
Generate synthesis scripts and retrieve synthesis results



