HDL test bench

Enable or disable HDL test bench generation

Model Configuration Pane: HDL Code Generation / Test Bench

Description

The HDL test bench parameter enables or disables the HDL test bench generation.

The code generator creates a HDL test bench by running a Simulink^® simulation that captures input vectors and expected output data for your DUT. This test bench is the default test bench that HDL Coder™ generates for your model. If you have not already generated code for your model, running HDL test bench generation also generates code for your DUT.

Specify your HDL simulator in the Simulation tool menu. HDL Coder generates build-and-run scripts for the simulator that you specify.

Dependencies

To enable this parameter:

• Select Generated model.

• Set Generate HDL for to the DUT.

• Set Simulation tool as any value except Synopsys VCS.

Settings

on (default) | off

on

Enable generation of HDL test bench code.

off

Do not generate HDL test bench code. Use this parameter when you use an alternative test bench.

Tips

To set this property, use the makehdltb function. For example, to generate a HDL test bench for the sfir_fixed/symmetric_fir subsystem, pass the DUT as an argument to the makehdltb function:

makehdltb("sfir_fixed/symmetric_fir")

Programmatic Use

Parameter: GenerateHDLTestBench

Type: character vector

Value: 'on' | 'off'

Default: 'on'

Version History

Introduced in R2012a