Output data type

HDL data type for the output ports of the model

Model Configuration Pane: Global Settings / Ports

Description

Specify the HDL data type for the output ports of the model.

Dependencies

This option is enabled when the target language (specified by the Language option) is VHDL^®.

Settings

Same as input type (default) | std_logic_vector | signed/unsigned

For VHDL, the options are:

Default: Same as input type

Same as input type

Specifies that output ports of the model have the same type specified by Input data type.

std_logic_vector

Specifies VHDL type STD_LOGIC_VECTOR as the data type of the output port.

signed/unsigned

Specifies VHDL type SIGNED or UNSIGNED as the data type of the output port.

For Verilog^® and SystemVerilog, the options are:

Default: wire

In generated Verilog and SystemVerilog code, the data type for all ports is 'wire', and cannot be modified. Therefore, Output data type is disabled when the target language is Verilog or SystemVerilog.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: OutputType

Type: character vector

Value: (for VHDL)'std_logic_vector' | 'signed/unsigned', (for Verilog) 'wire'

Default: If the property is left unspecified, output ports have the same type specified by InputType.

Version History

Introduced in R2012a