writePort

Write data to a DUT port from MATLAB

Syntax

writePort(hFPGA, portName, data)

writePort(hFPGA, portName,data,InterfaceID)

valid=writePort(hFPGA, portName, data)

Description

writePort(hFPGA, portName, data) casts the input data, specified by data, to the data type of the port, portName, and dispatches to the interface mapped to that port to write the data. Before you write the data, set up a connection from MATLAB^® to the target FPGA or SoC device, hFPGA, and then use the mapPort function to map the portName to that interface.

writePort(hFPGA, portName,data,InterfaceID) casts the input data, specified by data, to the data type of the overlapped port, portName, by using the optional InterfaceID argument and dispatches to the interface mapped to that port to write the data.

valid=writePort(hFPGA, portName, data) returns a valid signal to indicate that the data write was completed.

Examples

Write Data to DUT Port Mapped to AXI4 Slave Interfaces

This example shows how to write data to the DUT ports that are mapped to AXI4 slave interfaces.

Create an fpga object with Xilinx as Vendor.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

   Top-Level Properties

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interface to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "AXI4-Lite", ...
	"BaseAddress", 0xA0000000, ...
	"AddressRange", 0x10000);

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

hPort_h_in1 = hdlcoder.DUTPort("h_in1", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Lite", ...
	"IOInterfaceMapping", "0x100");

Map the DUT port objects to the AXI4 slave interface and then write data by using the writePort function.

mapPort(hFPGA, hPort_h_in1);

writePort(hFPGA, "h_in1", 5);

Write Data to DUT Port Mapped to AXI4-Stream Interfaces

This example shows how to write data to the DUT ports that are mapped to AXI4-Stream interfaces.

Create an object for the target device.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Stream interface to the hFPGA object by using the addAXI4StreamInterface function.

%% AXI4-Stream
addAXI4StreamInterface(hFPGA, ...
	"InterfaceID", "AXI4-Stream", ...
	"WriteEnable", true, ...
      "ReadEnable", true, ...
	"WriteFrameLength", 1024, ...
	"ReadFrameLength", 1024);

Specify the DUT port as an hdlcoder.DUTPort object array and then map the port to the AXI4-Stream interface.

hPort = hdlcoder.DUTPort("x_in", ...
	"Direction", "IN", ...
	"DataType", numerictype(1,16,10), ...
	"Dimension", [1 1], ...
	"IOInterface", "AXI4-Stream");

Map the DUT port objects to the AXI4-Stream interface and then write data by using the writePort function.

mapPort(hFPGA, hPort);

writePort(hFPGA, "x_in", sin(linspace(0, 2*pi, 1024)));

Write to a DUT with Overlapping Port Names

This example shows you how to write data to a DUT with overlapping port names by using the InterfaceID argument.

Create an fpga object with Xilinx as Vendor.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

   Top-Level Properties

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 slave interfaces to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "DUT1_Registers");

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

p = hdlcoder.DUTPort("myPort", ...
	"Direction", "IN", ...
	"IOInterface", "AXI4-Lite", ...
	"IOInterfaceMapping", "0x100");

Add the AXI4 slave interfaces to the hFPGA object by using the addAXI4SlaveInterface function.

%% AXI4 Slave
addAXI4SlaveInterface(hFPGA, ...
	"InterfaceID", "DUT2_Registers");

Specify the DUT ports in the HDL IP core as an hdlcoder.DUTPort object array and then map the port to the AXI4 slave interface.

p = hdlcoder.DUTPort("myPort", ...
	"Direction", "IN", ...
	"IOInterface", "AXI4-Lite", ...
	"IOInterfaceMapping", "0x100");

Map the DUT port objects to the AXI4 slave interface and then write data by using the writePort function with the optional InterfaceID argument.

mapPort(hFPGA, p);

writePort(hFPGA, "DUT2_Registers", "myPort", 5);

Input Arguments

hFPGA — Target FPGA object

fpga object

fpga object for the target vendor, specified as an fpga object.

portName — DUT port name

string

DUT port name, specified as a string. You create the DUT port as an hdlcoder.DUTPort object array. Before you specify the portName, you must have mapped the port to an AXI interface by using the mapPort function.

data — Input data

Scalar (default) | Vector

Input data to write to the DUT port, PortName, specified as a scalar or a vector.

InterfaceID — Name of FPGA interface

"" | string

Name of FPGA interface, specified as a string.

Output Arguments

valid — Write data valid true or false result

true | false | boolean

Write data valid, returned as true or false of data type boolean. This argument is only available when the WriteTimeout value is set to a finite value and the port is mapped to an AXI4-Stream interface.

Version History

Introduced in R2020b