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Guidelines for Speed and Area Optimizations

Guidelines for optimizing your design for speed and area for deployment to the target FPGA device

The HDL modeling guidelines are a set of recommended guidelines for creating Simulink® models, MATLAB Function blocks, and Stateflow® charts for code generation with HDL Coder™. In addition to providing architectural guidance, because the generated code targets hardware platforms such as FPGAs, ASICs, and SoCs, you can use these guidelines to optimize your design for speed or area on the target hardware.

Topics

List of Guidelines and Severity Levels

Guidelines for Speed and Area Optimizations - By Numbered List

List of speed and area optimization guidelines in ascending order of Guideline ID.

HDL Modeling Guidelines Severity Levels

Various severity levels associated with the HDL modeling guidelines and their description.

Guidelines for Area Optimizations

Resource Sharing Settings for Various Blocks

Recommended settings for using the resource sharing optimization effectively for various blocks.

Resource Sharing of Subsystems and Floating-Point IPs

Recommended settings for using the resource sharing optimization effectively for Subsystems and floating-point IPs.

Guidelines for Speed Optimizations

Distributed Pipelining and Clock-Rate Pipelining Guidelines

The code generator introduces registers when you specify certain block implementations or use certain settings.

Insert Distributed Pipeline Registers for Blocks with Vector Data Type Inputs

Recommended settings for using the distributed pipelining optimization effectively with vector inputs.

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