Generate Instantiable Code for Functions

You can use the Generate instantiable code for functions option to generate a VHDL^® entity, or Verilog^® or SystemVerilog module for each function. The software generates code for each entity or module in a separate file.

How to Generate Instantiable Code for Functions

To enable instantiable code generation for functions in the UI:

1. In the HDL Workflow Advisor, select the HDL Code Generation task.

2. In the Advanced tab, select Generate instantiable code for functions.

To enable instantiable code generation for functions programmatically, in your coder.HdlConfig object, set the InstantiateFunctions property to true. For example, to create a coder.HdlConfig object and enable instantiable code generation for functions:

hdlcfg = coder.config('hdl');
hdlcfg.InstantiateFunctions = true;

Generate Code Inline for Specific Functions

If you want to generate instantiable code for some functions but not others, enable the option to generate instantiable code for functions, and use coder.inline. See coder.inline for details.

Limitations for Instantiable Code Generation for Functions

The software generates code inline when:

• Function calls are within conditional code or for loops.

• Any function is called with a nonconstant struct input.

• The function has state, such as a persistent variable, and is called multiple times.

• There is an enumeration anywhere in the design function.