Specify Bidirectional Ports
You can specify bidirectional ports for Subsystem blocks with black box
implementation. In the generated code, the bidirectional ports have the Verilog®, SystemVerilog or VHDL®
inout
keyword.
In the FPGA Turnkey workflow, you can use the bidirectional ports to connect to external RAM.
Requirements
The bidirectional port must be a black box subsystem port.
There must be no logic between the bidirectional port and the corresponding top-level DUT subsystem port. Otherwise, the generated code does not compile.
How To Specify a Bidirectional Port
To specify a bidirectional port using the UI:
In the black box Subsystem, right-click the Inport or Outport block that represents the bidirectional port. Select HDL Code > HDL Block Properties.
For BidirectionalPort, select
on
.
To specify a bidirectional port at the command line, set the
BidirectionalPort
property to 'on'
using
hdlset_param
or makehdl
.
For example, suppose you have a model, my_model
, that
contains a DUT subsystem, dut_subsys
, and the DUT subsystem
contains a black box subsystem, blackbox_subsys
. If
blackbox_subsys
has an Inport,
input_A
, specify input_A
as
bidirectional by
entering:
hdlset_param('mymodel/dut_subsys/blackbox_subsys/input_A','BidirectionalPort','on');
Limitations
In the FPGA Turnkey workflow, in the Target platform interfaces table, you must map a bidirectional port to either
Specify FPGA Pin {’LSB’,...,’MSB’}
or one of the other interfaces where the interface bitwidth exactly matches your bidirectional port bitwidth.For example, you can map a 32-bit bidirectional port to the
Expansion Headers J6 Pin 2-64[0:31]
interface.You cannot generate a Verilog or SystemVerilog test bench if there is a bidirectional port within your DUT subsystem.
HDL Coder™ does not support bidirectional ports for masked subsystems that use
BlackBox
as the HDL Architecture.Simulink® does not support bidirectional ports, so you cannot simulate the bidirectional behavior in Simulink.