Verification with FPGA hardware
Run a Simulink® or MATLAB® simulation that is synchronized with an HDL design running on a Xilinx® FPGA board.
- FPGA-in-the-Loop Simulation
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
- FPGA-in-the-Loop Simulation Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor.